search for: middleend

...emoved) - Even when merging the two, I believe it is still possible to implement a target without linking to lib/CodeGen by returning nullptr for the various methods related to CodeGen. - The split would give some notion of an internal CodeGen interface and an external interface visible to frontend/middleend etc. - The code gets simpler when merging the two and we have to document/explain less. - Matthias -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20171002/7435e622/attachment.html>

...end "4". > Someone needs to implement how to apply the addend 4 to the addend 0xea000000. That's what I meant by manipulating addends. You could do that by relying on MC to do it (your proposal), or you can rely on the linker to do it (my proposal). With my proposal, the frontend/middleend controls section data > indirectly, meaning the actual final section data does not appear as > an IR constant, but we can still get whatever constant we want. On the > other hand, this representation is better for optimizations (instead > of a magic constant 0xfffffe you have a transpar...

...tion into another IR). > > I'm dubious of this need, but as long as it doesn't add any overhead to the resultant code I'm good. -eric > -Hal > > > - The split would give some notion of an internal CodeGen interface and an > external interface visible to frontend/middleend etc. > - The code gets simpler when merging the two and we have to > document/explain less. > > - Matthias > > > _______________________________________________ > LLVM Developers mailing listllvm-dev at lists.llvm.orghttp://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev &g...

Hi LLVM developers, I am implementing Loong Language[1] using Clang FrontEnd and LLVM MiddleEnd. I add `wire`[2] Builtin Type, and clang is able to parse very small testcase fulladder[3] but failed to work for 10+K loc RISCV E203 project[4]: Loongson clang version 7.0.0 (git at github.com:Loong-Language/loong-clang.git 8f7e826f27abbe12ea08d9563490298c38d3adc1) (git at github.com:Loong-...

...le of a rela relocation which uses both r_addend and > the > > underlying value in the object file? > > The point of .rela is to allow addends that do not fit into the > underlying value. Such addends can not be expressed as the third > argument of reloc(), either. And IMHO the middleend should not worry > about such details. > Something has to worry about them at some point. If a frontend/pass is creating relocations, then it will need to know at least vaguely which addend it wants. If that's the case, we can make it the single component responsible for worrying about t...

...;t have access to the source code right now, can you clarify if the backend can tail call when the IR didn't mark the call as such, or if what you're referring to is "not honoring the tail call From the IR and demoting to a normal call? > > The backend does only tail call if the middleend marked the call with the "tail" or "musttail" marker. But that happens for most calls. We can only really transform a franction of those into real tail calls later. Thanks, so back to my original point: if we have to disable the CSR optimization on function that “may be tail ca...

...i don't have access to the source code right now, can you clarify if the backend can tail call when the IR didn't mark the call as such, or if what you're referring to is "not honoring the tail call From the IR and demoting to a normal call? The backend does only tail call if the middleend marked the call with the "tail" or "musttail" marker. But that happens for most calls. We can only really transform a franction of those into real tail calls later. - Matthias -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm....

...he source code right now, can you clarify if > the backend can tail call when the IR didn't mark the call as such, or if > what you're referring to is "not honoring the tail call From the IR and > demoting to a normal call? > > > The backend does only tail call if the middleend marked the call with the > "tail" or "musttail" marker. But that happens for most calls. We can only > really transform a franction of those into real tail calls later. > > > Thanks, so back to my original point: if we have to disable the CSR > optimization on...

Sent from my iPhone > On Jun 28, 2016, at 2:27 PM, Matthias Braun <matze at braunis.de> wrote: > > >> On Jun 28, 2016, at 10:09 AM, Mehdi Amini via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> >> >> Sent from my iPhone >> >>> On Jun 28, 2016, at 12:53 PM, vivek pandya <vivekvpandya at gmail.com> wrote:

...oncurrent. VHDL code could also be simulated by a simulator in which case the concurrent instructions are of course executed serially because the VHDL code is compiled in this case to assembly instructions. I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations. I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifying GH...

...> VHDL code could also be simulated by a simulator in which case the concurrent instructions are of course executed serially because the VHDL code is compiled in this case to assembly instructions. > I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations. > I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifyi...

On Fri, Oct 7, 2016 at 12:20 PM, Evgenii Stepanov <eugeni.stepanov at gmail.com > wrote: > I've tried implementing some of the alternatives mentioned in this > thread, and so far I like this syntax the most: > > i32 reloc (29, void ()* @f, 3925868544) > ; 29 = 0x1d = R_ARM_JUMP24 > ; 3925868544 = 0xea000000 > > Note the zeroes in the relocated data instead of

...> VHDL code could also be simulated by a simulator in which case the concurrent instructions are of course executed serially because the VHDL code is compiled in this case to assembly instructions. > I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations. > I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifyi...