search for: micromip

Hello Daniel, At the moment we are preparing the patch for disassembling microMIPS 16 bit instructions and it will be on Phabricator tomorrow or on Wednesday. Functionality is implemented in MipsDisassembler::getInstruction where first two bytes are read and decodeInstruction is called with DecoderTableMicroMips16 and only if it fails we read 4 bytes and call decodeInstruction...

Hi, We have this line in micromips-16-bit-instructions.s # CHECK-EB: addu16 $6, $17, $4 # encoding: [0x07,0x42] However, when I check this with llvm-mc, like below, I dont get back the assembly. This is against the latest LLVM code. What is wrong here? Thanks, Jun $ echo "0x07,0x42"|./Release+Asserts/bin/llv...

...sor extenasions to mips32 and mips64. So usually you would build a mips32 or mips64 compiler and then add -mips16 to the command line. Right now, there are no implementations of micro mips or mips16 with mips 64, though architecturally it is defined. So the options would be: -mips16 -mips32 -micromips -mips64 With the implications the -mips16 and -micromips both imply mips32 as the base architecture. mips32 and mips64 have mostly the same instruction encoding (difference being the size of the registers). Ideally you would want: standardencoding = !mips16 & !micrormips then standarden...

Hi Rui, Rafael, You are reviewers of two MIPS related patches for LLD linker: - Handle cross-mode (regular <-> microMIPS) jumps https://reviews.llvm.org/D40147 - Multi-GOT implementation https://reviews.llvm.org/D31528 Both patches implement essential part of MIPS architecture. microMIPS is something like ARM Thumb. Multi-GOT support required to link any rather complex application for MIPS targets. For example...

...to the one we had in LLVM 3.6.2. 2. Read-only exception tables have broken compatibility with the ~2 year old gcc toolchains I was using for release testing cross compilation. This isn't a problem for most test-suite runs since we can just update the assembler but is causing trouble for microMIPS. More recent toolchains lack the microMIPS multilib I was using and migrating to the new one is causing link failures. These failures are related to ELF header bits specifying the SNaN/QNaN encodings to be IEEE754-1985 or IEEE754-2008 compliant. I suspect the -mnan=2008 isn't reaching the asse...

...-gnu-ubuntu-14.04.tar.xz (cross > > > compiling for Mips): > > > Still running > > > > Of what's completed so far I'm seeing a lot of timeouts that weren't in rc1. > > Mostly on the TSVC tests. It's looks like the qemu update that was needed for microMIPS has introduced a bug in some of the other configs. I've successfully re-run some of the failing tests with the previous qemu. I'm re-running the rest overnight and it should be mostly finished by the morning.

...ody (if exists) or not. I wonder if there was some progress on that. On Mon, Apr 23, 2018 at 10:28 AM Simon Atanasyan <simon at atanasyan.com> wrote: > Hi Rui, Rafael, > > You are reviewers of two MIPS related patches for LLD linker: > > - Handle cross-mode (regular <-> microMIPS) jumps > https://reviews.llvm.org/D40147 > > - Multi-GOT implementation > https://reviews.llvm.org/D31528 > > Both patches implement essential part of MIPS architecture. microMIPS > is something like ARM Thumb. Multi-GOT support required to link any > rather complex app...

...VM 3.6.2. > > 2. Read-only exception tables have broken compatibility with the ~2 > year old gcc toolchains I was using for release testing cross compilation. > This isn't a problem for most test-suite runs since we can just update the > assembler but is causing trouble for microMIPS. More recent toolchains lack > the microMIPS multilib I was using and migrating to the new one is causing > link failures. These failures are related to ELF header bits specifying the > SNaN/QNaN encodings to be IEEE754-1985 or IEEE754-2008 compliant. I suspect > the –mnan=2008 isn'...

Hi all, I plan to deprecate the experimental microMIPS64R6 backend for the 5.0 release and remove it after the release. Currently there are no CPUs that use that particular sub-ISA which makes it difficult to justify the maintenance and parallel development effort. If there was a CPU design produced that did use microMIPS64R6, the backend could be r...

...to the one we had in LLVM 3.6.2. 2. Read-only exception tables have broken compatibility with the ~2 year old gcc toolchains I was using for release testing cross compilation. This isn't a problem for most test-suite runs since we can just update the assembler but is causing trouble for microMIPS. More recent toolchains lack the microMIPS multilib I was using and migrating to the new one is causing link failures. These failures are related to ELF header bits specifying the SNaN/QNaN encodings to be IEEE754-1985 or IEEE754-2008 compliant. I suspect the –mnan=2008 isn't reaching the asse...

...> 2. Read-only exception tables have broken compatibility with the ~2 > > year old gcc toolchains I was using for release testing cross compilation. > > This isn't a problem for most test-suite runs since we can just update the > > assembler but is causing trouble for microMIPS. More recent toolchains > lack > > the microMIPS multilib I was using and migrating to the new one is causing > > link failures. These failures are related to ELF header bits specifying the > > SNaN/QNaN encodings to be IEEE754-1985 or IEEE754-2008 compliant. I > suspect &g...

I'm implementing this ability to switch between mips16 and mips32 on a per function basis. One issue that I've run into is regarding the DAGToDAGIsel pass. We have a different subclass for mips16 and non mips16 ( conceivably later there could be a separate one for micromips). I need to run a different pass depending on whether it's mips16 or mips32. My initial plan was to create a dummy ModuleDAGToDAGIsel whose sole purpose in it's run machine function was to decide which one of these to run and then call an appropriate DAGToDAGIIsel but I'm running i...

Micro mips is really 100% .s compatible with mips32. There are no register field size constraints and such. It's a strict superset of mips32. For the gcc port, the assembler is basically the only thing we changed. The gcc port was just adding the ".micromips" directive to the .s file and maybe some tiny driver work. That is the quandary. The entire .td file would have to be duplicated and just the instruction binary encoding changed. Mips16 ,which is what I am almost finished with (base port), is more different and has a lot of restrictions...

...gage. The small bit of baggage that is giving me fits is that MipsELFObjectWriter needs to know the relocation model (static,pic,cpic), whether we are using xgot (-mgot), which abi (old,new), which architecture (32r[123],64[123]), which if any coprocessor or extention instructions are used (mips16,micromips,etc.). I shouldn't have to muck with base classes to handle esoteric target specific issues such as these. <target>ELFObjectWriteris used for direct object output whether directly from the codegen or from the llvm-mc assembler. The grand idea was to use MipsSubtarget because it has al...

...o need to split each opcode with a 16-bit variant (say, ADD) into two versions: the 16-bit version with constrained input/output registers, and the 32-bit version with unconstrained registers. Since this distinction doesn't exist in mips32, you'll want to have them entirely guarded under a micromips subtarget. This really is almost exactly the same situation as Thumb2 on ARM. I strongly suggest you look at how it's implemented there. --Owen On Sep 5, 2012, at 9:45 PM, reed kotler <rkotler at mips.com> wrote: > The problem is that everything about the mips32 and micro mips 1...

...dicates are overriden by a derived class, it overwrites the previous definition. There is no way, it seems, to add to an existing list as you further derive classes. So for example, for mips we would want to have several predicates for the output format of instructions, i.e. (standard, mips16, micromips) But if we have such predicates in a base class, then if some later class wants to add additional ones, then they have to list the ones from the base class again. This seems to be very error prone. Is there some basic convention that the ARM port uses to keep all of this straight? Tia. Reed

...x this is to retrieve data associated with the pass and change it. This would require some change to the pass infrastructure. The pointers are to classes which are derived classes, currently we have a mips16 and a non mips16 variant but there could be others ( not sure how will handle this with micromips at this time). Thoughts?

...bility to switch between mips16 and mips32 on a >> per function basis. >> >> One issue that I've run into is regarding the DAGToDAGIsel pass. >> >> We have a different subclass for mips16 and non mips16 ( conceivably >> later there could be a separate one for micromips). >> >> >> I need to run a different pass depending on whether it's mips16 or >> mips32. >> >> My initial plan was to create a dummy ModuleDAGToDAGIsel whose sole >> purpose in it's run machine function was to decide which one of these >> to...

...e we had in LLVM 3.6.2. > > 2. Read-only exception tables have broken compatibility with the ~2 year old gcc toolchains I was using for release testing cross compilation. This isn't a problem for most test-suite runs since we can just update the assembler but is causing trouble for microMIPS. More recent toolchains lack the microMIPS multilib I was using and migrating to the new one is causing link failures. These failures are related to ELF header bits specifying the SNaN/QNaN encodings to be IEEE754-1985 or IEEE754-2008 compliant. I suspect the –mnan=2008 isn't reaching the asse...

...of baggage that is giving me fits is that MipsELFObjectWriter > needs to know the relocation model (static,pic,cpic), whether we are using > xgot (-mgot), which abi (old,new), which architecture (32r[123],64[123]), > which if any coprocessor or extention instructions are used > (mips16,micromips,etc.). So the mips assembler has command line options like -fPIC? Cheers, Rafael