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2019 Nov 25
2
Tablegen PAT limitation?
...p;nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Thanks. Looking at the InOperandList, the rs1, rbase, etc. have register class prefixes, e.g. MGPR:$rs1.&nbsp; In the pattern they don’t have them.&nbsp; The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands. Could you change the pattern to &nbsp; &nbsp; [(OpNode (v1i16 MGPR:$r...
2019 Nov 22
2
Tablegen PAT limitation?
...ng DecoderNamespace = ""; &nbsp; list<Predicate&gt; Predicates = []; &nbsp; string DecoderMethod = ""; &nbsp; bit hasCompleteDecoder = 1; &nbsp; string Namespace = "RPP"; &nbsp; dag OutOperandList = (outs); &nbsp; dag InOperandList = (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift); &nbsp; string AsmString = "STORE $rs1, [$rbase + ( $roffset << $rshift )]"; &nbsp; list<dag&gt; Pattern = [(store (v1i16 ?:$rs1), (add (v1i32 (bitconvert (i32 ?:$rbase))), (shl (v1i32 (sext (v1i16 ?:$roffset))), (v1i...
2019 Nov 21
2
Tablegen PAT limitation?
Hi Krzysztof, Today I try it on llvm9.0.0 version. &nbsp; def bos : RPPInstMMEMrr<OPC_STORE, &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift), &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1, [$rbase + ( $roffset << $rshift )]", &nbsp; //&nbsp; &nbsp; &nbsp; &nbsp; &...
2019 Nov 20
4
Tablegen PAT limitation?
...lvm.org&gt; Subject: [EXT] [llvm-dev] Tablegen PAT limitation? &nbsp; Hello, &nbsp; def GPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add &nbsp; &nbsp; IA, IB, IC, ID, IE, IF, IG, IH &nbsp; )&gt;; &nbsp; def MGPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add &nbsp; &nbsp; IA, IB, IC, ID, IE, IF, IG, IH &nbsp; )&gt;; &nbsp; def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add &nbsp; &nbsp; DS0, DS1, DS2, DS3, DS4, DS5, D...
2017 Jan 13
2
NDS32 V3 backend
Hi all, On behalf of Andes Technology Corp, I am proposing a backend targeting the NDS32 V3 ISA. NDS32 V3 ISA is a 16/32 bit mixed instruction set architecture that developed By AndesTech. You can find more information at the Andes website <http://www.andestech.com/>, and reference AndeStar ISA Manual (V3 ISA) from document download page <http://www.andestech.com/product.php?cls=9>.