search for: mgather

Hello, my target support maximum gather of v64i32....i want to lower all the greater gathers to v64i32. for this i used; setOperationAction(ISD::MGATHER, MVT::v128i32, Expand); but i am getting error; LLVM ERROR: Cannot select: t4257: v128i32,ch = masked_gather<LD512[<unknown>](align=4)(tbaa=<0x30e7c78>)> t0, undef:v128i32, t4394, TargetConstant:i64<0>, t4312 t1061: v128i32 = undef t4394: v128i1 = BUILD_VEC...

...masked gather > SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>, > SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1> > ]>; > > def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, > [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; > > > Also, we need to make the operand $wsi a memory operand (otherwise we get the > difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v1...

...<2, 3, [ // masked gather SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>, SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1> ]>; def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; Also, we need to make the operand $wsi a memory operand (otherwise we get the difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v128i16' needs to...

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure: "llvm/utils/TableGen/CodeG...

...dst|$dst, $src}", [(set VR_2048:$dst, (v64i32 (masked_gather addr:$src)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B addr:$src)>; Also i wrote this line in isellowering.h setOperationAction(ISD::MGATHER, MVT::v64i32, Legal); But I am getting following error: llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:2134: llvm::TreePatternNode *llvm::TreePattern::ParseTreePattern(llvm::Init *, llvm::StringRef): Assertion `New->getNumTypes() == 1 && "FIXME: Unhandled"...

..., (v64i32 (masked_gather >> addr:$src)))], >> IIC_MOV_MEM>, TA; >> def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B addr:$src)>; >> >> Also i wrote this line in isellowering.h >> >> setOperationAction(ISD::MGATHER, MVT::v64i32, >> Legal); >> >> But I am getting following error: >> >> llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:2134: >> llvm::TreePatternNode *llvm::TreePattern::ParseTreePattern(llvm::Init *, >> llvm::StringRef): Assertion `New->...

...xing up many code-paths that didn’t yet support scalable vectors. Most of that functionality already made it into LLVM 11. * In anticipation of auto-vectorization we started adding support for SVE/SVE2 code generation from regular LLVM IR instructions. Most common ISD nodes are now supported, with MGATHER/MSCATTER and strict FP reductions still work in progress. For this effort, we’ve needed to fix up type legalization in SelectionDAG to work on scalable vectors along the way. See for example https://reviews.llvm.org/D85754 and https://reviews.llvm.org/D79587. * To emit code for fixed-width vectors...

...C_MOV_MEM>, TA; >>>>>> def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B addr:$src)>; >>>>>> >>>>>> Also i wrote this line in isellowering.h >>>>>> >>>>>> setOperationAction(ISD::MGATHER, >>>>>> MVT::v64i32, Legal); >>>>>> >>>>>> But I am getting following error: >>>>>> >>>>>> llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:2134: >>>>>> llvm::TreePatternNode *llvm::TreePa...