Displaying 7 results from an estimated 7 matches for "mflo".
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2012 Sep 16
1
[LLVMdev] Pattern class
Here is a simple place I wanted to use it.
...
On multiply, the result implicit is placed in a 64 bit hi/lo register.
//
// Format: MFLO rx MIPS16e
// Purpose: Move From LO Register
// To copy the special purpose LO register to a GPR.
//
def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
let Uses = [LO];
let neverHasSideEffects = 1;
}
//
// Pseudo Instruction for mult
//
def MultRxRy16: FMULT16_ins<"mult...
2012 Sep 16
0
[LLVMdev] Pattern class
What have you tried?
On Sun, Sep 16, 2012 at 3:34 PM, Kotler, Reed <rkotler at mips.com> wrote:
> This Pattern class says it's possible but seems just to not work or maybe I'm using it incorrectly.
>
> Probably I will go and fix it when I'm done with mips16.
>
>
> ________________________________________
> From: Hal Finkel [hfinkel at anl.gov]
> Sent:
2012 Sep 16
2
[LLVMdev] Pattern class
This Pattern class says it's possible but seems just to not work or maybe I'm using it incorrectly.
Probably I will go and fix it when I'm done with mips16.
________________________________________
From: Hal Finkel [hfinkel at anl.gov]
Sent: Sunday, September 16, 2012 10:59 AM
To: Anton Korobeynikov
Cc: Kotler, Reed; LLVM-Dev [llvmdev at cs.uiuc.edu]
Subject: Re: [LLVMdev] Pattern
2013 Oct 08
0
[LLVMdev] Subregister liveness tracking
...produced by another mthi/lo. So I don't think making
mthi/lo clobber the other half would work.
For example, this is an illegal sequence of instructions, where instruction
3 makes $hi unpredictable:
1. mult $lo<def>, $hi<def>, $2, $3 // $lo<def>, $hi<def> = $2 * $3
2. mflo $4, $lo<use> // $4 <- $lo
3. mtlo $lo<def>, $6 // $lo <- $6. effectively clobbers $hi too.
4. mfhi $5, $hi<use> // $5 <- $hi
5. mthi $hi<def>, $7 // $hi <- $7
6. madd $lo<def>, $hi<def>, $8, $9, $lo<use>, $hi<use> // $lo<def>,
$hi<...
2013 Oct 09
4
[LLVMdev] Subregister liveness tracking
...d can’t really be expressed like that in the current RA framework I think.
>
> For example, this is an illegal sequence of instructions, where instruction 3 makes $hi unpredictable:
>
> 1. mult $lo<def>, $hi<def>, $2, $3 // $lo<def>, $hi<def> = $2 * $3
> 2. mflo $4, $lo<use> // $4 <- $lo
> 3. mtlo $lo<def>, $6 // $lo <- $6. effectively clobbers $hi too.
> 4. mfhi $5, $hi<use> // $5 <- $hi
> 5. mthi $hi<def>, $7 // $hi <- $7
> 6. madd $lo<def>, $hi<def>, $8, $9, $lo<use>, $hi<use> // $l...
2013 Oct 08
2
[LLVMdev] Subregister liveness tracking
Currently it will always spill / restore the whole vreg but only
spilling the parts that are actually live would be a nice addition in
the future.
Looking at r192119': if "mtlo" writes to $LO and sets $HI to an
unpredictable value, then it should just have an additional (dead) def
operand for $hi, shouldn't it?
Greetings
Matthias
Am 10/8/13, 11:03 AM, schrieb Akira
2014 May 10
6
[LLVMdev] Replacing Platform Specific IR Codes with Generic Implementation and Introducing Macro Facilities
On 10 May 2014, at 13:53, Tim Northover <t.p.northover at gmail.com> wrote:
> It doesn't make sense for everything though, particularly if you want
> target-specific IR to simply not exist. What would you map ARM's
> "ldrex" to on x86?
This isn't a great example. Having load-linked / store-conditional in the IR would make a number of transforms related to