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[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...mpleValueType which can represents a 96-bit register. Thus, my question is: 1) Does current LLVM backend supports this H/W? 2) If yes, how can I write the type of the register class in my .td file? (Which value should I fill in the following 'XXX' ?) def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...my question is: > > > 1) Does current LLVM backend supports this H/W? > > 2) If yes, how can I write the type of the register class in my .td   > > file? > > > (Which value should I fill in the following 'XXX' ?) > > def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3,   > > R4, R5, R6, R7, R8, R9, > >                                                    R10, R11, R12,   > > R13, R14, R15, R16, R17, R18, R19, > >                                                    R20, R21, R22,   > > R23, R24, R25, R2...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...register. > > Thus, my question is: > > 1) Does current LLVM backend supports this H/W? > 2) If yes, how can I write the type of the register class in my .td > file? > > (Which value should I fill in the following 'XXX' ?) > def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > R4, R5, R6, R7, R8, R9, > R10, R11, R12, > R13, R14, R15, R16, R17, R18, R19, > R20, R21, R22, > R23, R24, R25, R26, R27, R28, R29, >...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...> >>> 1) Does current LLVM backend supports this H/W? >>> 2) If yes, how can I write the type of the register class in my .td >>> file? >> >>> (Which value should I fill in the following 'XXX' ?) >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>> R4, R5, R6, R7, R8, R9, >>> R10, R11, R12, >>> R13, R14, R15, R16, R17, R18, R19, >>> R20, R21, R22, >>> R23, R24...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...> >>> 1) Does current LLVM backend supports this H/W? >>> 2) If yes, how can I write the type of the register class in my .td >>> file? >> >>> (Which value should I fill in the following 'XXX' ?) >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>> R4, R5, R6, R7, R8, R9, >>> R10, R11, R12, >>> R13, R14, R15, R16, R17, R18, R19, >>> R20, R21, R22, >>> R23, R24...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...; 1) Does current LLVM backend supports this H/W? > >>> 2) If yes, how can I write the type of the register class in my .td > >>> file? > > >>> (Which value should I fill in the following 'XXX' ?) > >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > >>> R4, R5, R6, R7, R8, R9, > >>>                                                    R10, R11, R12, > >>> R13, R14, R15, R16, R17, R18, R19, > >>>                                                    R20, R21, R22, &...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...this H/W? >>>>> 2) If yes, how can I write the type of the register class in >>>>> my .td >>>>> file? >> >>>>> (Which value should I fill in the following 'XXX' ?) >>>>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>>>> R4, R5, R6, R7, R8, R9, >>>>> R10, R11, R12, >>>>> R13, R14, R15, R16, R17, R18, R19, >>>>> R20,...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...; 1) Does current LLVM backend supports this H/W? > >>> 2) If yes, how can I write the type of the register class in my .td > >>> file? > > >>> (Which value should I fill in the following 'XXX' ?) > >>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > >>> R4, R5, R6, R7, R8, R9, > >>>                                                    R10, R11, R12, > >>> R13, R14, R15, R16, R17, R18, R19, > >>>                                                    R20, R21, R22, &...
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...this H/W? >>>>> 2) If yes, how can I write the type of the register class in >>>>> my .td >>>>> file? >> >>>>> (Which value should I fill in the following 'XXX' ?) >>>>> def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, >>>>> R4, R5, R6, R7, R8, R9, >>>>> R10, R11, R12, >>>>> R13, R14, R15, R16, R17, R18, R19, >>>>> R20,...