search for: memory_order_relaxed

...e Developers, We recently ran into a problem building clang because some of the definitions in sanitizer_common conflicted with system definitions and later another system header was trying to use the system definition: .../usr/include/libkern/OSAtomicDeprecated.h:756:17: error: reference to 'memory_order_relaxed' is ambiguous __theAmount, memory_order_relaxed) + __theAmount); ^ .../usr/bin/../include/c++/v1/atomic:548:5: note: candidate found by name lookup is 'std::__1::memory_order::memory_order_relaxed' memory_order_relaxed, memory_order_consume, memory_order_acquire, ^ ../src/projects/compi...

...building clang because some of the >> definitions in sanitizer_common conflicted with system definitions and later >> another system header was trying to use the system definition: >> >> .../usr/include/libkern/OSAtomicDeprecated.h:756:17: error: reference to >> 'memory_order_relaxed' is ambiguous >> __theAmount, memory_order_relaxed) + __theAmount); >> ^ >> .../usr/bin/../include/c++/v1/atomic:548:5: note: candidate found by name >> lookup is 'std::__1::memory_order::memory_order_relaxed' >> memory_order_relaxed, memory_order_consume,...

Quoting Tim Northover <t.p.northover at gmail.com>: > On 24 April 2015 at 13:53, Tyler Denniston <tyler at csail.mit.edu> wrote: >> I'm wondering how I can create an atomic load and add instruction for >> floating point values. If I use IRBuilder::CreateAtomicRMW() I get the >> error message: "atomicrmw operand must have integer type". > >

> } while (__c11_atomic_compare_exchange_weak( > addr, &oldval, newval, memory_order_seq_cst, memory_order_relaxed)); Actually, I think this condition is inverted. Should be "while (!_c11...". Sorry about that. Tim.

Hi All , We are looking at the C sample i.e extern int i,j; int test() { while(1) { i++; j=20; } return 0; } command used :(clang version 3.8.0-2ubuntu4 (tags/RELEASE_380/final) ) clang -S test.c -O2 the generated asm for x86 .L2: jmp .L2 we understand that,the infinite loop is not deterministic ,compiler is free to treat as that as UB and do aggressive

...romotion, are not always valid. Of course, the problem with this approach is that it is often the case that compiler/hardware cannot reorder accesses to gain optimal performance and in light of this C++0x allows values of type atomic to be accessed through a relaxed consistency model, e.g. x.load(memory_order_relaxed); x.store(something, memory_order_relaxed); In this case the compiler is free to order load/stores to x, in different threads, any why it feels fit. The full set of relaxed options are defined by the enumeration: typedef enum memory_order { memory_order_relaxed, memory_order_acquire, mem...

Dear testers, 7.0.0-rc1 was just tagged (from the branch at r338847). It's early in the release process, but I'd like to find out what the status is of the branch on our various platforms. Please run the test script, share the results, and upload binaries. Thanks, Hans

Hi Ben, Vacation is always a good thing. Hope you had a good one. In my mind, having a more general memory consistency model is going to be very useful in LLVM in the future. It is still a little unclear to me what we should support. I haven't looked at what C++ is considering for their model. Are they going to support different relaxations models like relaxing write to read or

Hello, I trying TSAN on Darwin on LLVM itself (sanitizing multi-threaded ThinLTO link). However I see two main issues on my debug build: 1) Statistics: the pre/post increment is not safe, it seems to be acknowledge in the code itself: // FIXME: This function and all those that follow carefully use an // atomic operation to update the value safely in the presence of // concurrent

Hi, what's the current status of the memory-ordered operations described in https://docs.google.com/Doc?docid=0AYWBeVVqyP7dZGRiNG1oeHpfMjJkejVnOThkZA&hl=en.&pli=1 i.e. the ones for "load acquire", "store release" etc. for C++0x atomics, not the older ones for the __sync intrinsics? The specification looks good - is it just waiting to be implemented? Al --

Hi All, I am reading about LLVM IR atomics (http://llvm.org/docs/Atomics.html) and get confused about the difference between "Unordered" and "Monotonic". In particular, I am not sure I understand the statement of "It essentially guarantees that if you take all the operations affecting a specific address, a consistent ordering exists.". For me, it means that for the

...y '/home/dim/llvm/7.0.0/rc1/Phase1/Release/llvmCore-7.0.0-rc1.obj/CMakeFiles/CMakeTmp' > > Source file was: > > #include <atomic> > #include <cstdint> > std::atomic<uint64_t> x (0); > int main() { > uint64_t i = x.load(std::memory_order_relaxed); > return 0; > } > > Phase2 CMake output: > > Performing C++ SOURCE FILE Test HAVE_CXX_ATOMICS64_WITHOUT_LIB failed with the following output: > Change Dir: /home/dim/llvm/7.0.0/rc1/Phase2/Release/llvmCore-7.0.0-rc1.obj/CMakeFiles/CMakeTmp > > Run B...