search for: memoperands

...6ISelLowering.cpp (working copy) @@ -6010,7 +6010,9 @@ for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); MIB.addReg(t2); - + assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); + (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); MIB.addReg(X86::EAX); @@ -6107,6 +6109,8 @@ for (int i=0; i <= lastAddrIndx; ++i) (*MIB).addOperand(*argOpers[i]); MIB.addReg(t3); + assert(mInstr->hasOneMemOperand() && "Unex...

...,23 @@ // If opcodes or number of operands are not the same then the two // instructions are obviously not identical. if (Other->getOpcode() != getOpcode() || - Other->getNumOperands() != getNumOperands()) + Other->getNumOperands() != getNumOperands() || + Other->memoperands_empty() != memoperands_empty()) return false; + if (!memoperands_empty()) { + // If we have mem operands, make sure that the sizes of the memoperands for each + // MI are the same. The values can be different, so lets only check the sizes. + // If the sizes between one of the memoper...

...r number of operands are not the same then the two > // instructions are obviously not identical. > if (Other->getOpcode() != getOpcode() || > - Other->getNumOperands() != getNumOperands()) > + Other->getNumOperands() != getNumOperands() || > + Other->memoperands_empty() != memoperands_empty()) > return false; > + if (!memoperands_empty()) { > + // If we have mem operands, make sure that the sizes of the memoperands for each > + // MI are the same. The values can be different, so lets only check the sizes. > + // If the sizes b...

Hi Quentin, I get following error from MachineVerifier: # End machine code for function f. *** Bad machine code: Missing mayLoad flag *** which comes from: // Check the MachineMemOperands for basic consistency. for (MachineMemOperand *Op : MI->memoperands()) { if (Op->isLoad() && !MI->mayLoad()) report("Missing mayLoad flag", MI); if (Op->isStore() && !MI->mayStore()) report("Missing mayStore flag", MI); } T...

...tBLX -> tBL. This triggered an assertion error with expensive checks turned on in MachineVerifier because the newly created tBL insn by Thumb1InstrInfo::foldMemoryOperandImpl had memory operands of LoadMI attached by TargetInstrInfo::foldMemoryOperand, which is done unconditionally: // Copy the memoperands from the load to the folded instruction. if (MI.memoperands_empty()) { NewMI->setMemRefs(MF, LoadMI.memoperands()) In this case, we don't want the memory loads to be added to MI from LoadMI. Should there be some mechanism for target specific foldMemoryOperandImpl hook to signal to foldMem...

...lowing code snippet taken from StackColoring::remapInstructions clears a mem operand if it can't guarantee whether the memoperand's underlying value aliases with the merged allocas: // Update the MachineMemOperand to use the new alloca. 522 for (MachineInstr::mmo_iterator MM = I->memoperands_begin(), .... // Climb up and find the original alloca. 532 V = GetUnderlyingObject(V); 533 // If we did not find one, or if the one that we found is not in our 534 // map, then move on. 535 if (!V || !isa<AllocaInst>(V)) { 536 // Clear...

...> and cached. >> >> BasicAA has a cache internally, but as far as I can tell, only to guard against recursion (and it is emptied after each query). Am I missing something? > > It's not clear to me how AA is used in codegen. I understand some information are transferred to memoperands during LLVM IR to SDISel conversion. Is AA actually being recomputed using LLVM IR during codegen? In general, when AA is used during codegen, it grabs the IR value from the machine memoperands, then runs normal IR-level alias analysis. The IR needs to stay around and be immutable. That’s why anyt...

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0; mem:LD4[<unknown>]   I checked for memoperands for this MachInst, which are not empty, as "has_empty()" returns false. When I check &quo...

...ddReg(OffReg); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); ++NumLDRDFormed; On Tue, Sep 7, 2010 at 1:31 PM, Bill Wendling <wendling at apple.com> wrote: > On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > > > I have two questions regarding MachineMemOperands and dependence > information. > > > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined > and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > > > (before optimization) > > %reg1033<def> = LDR %reg1030, %reg0, 4100...

...>>> >>> BasicAA has a cache internally, but as far as I can tell, only to guard against recursion (and it is emptied after each query). Am I missing something? >> >> It's not clear to me how AA is used in codegen. I understand some information are transferred to memoperands during LLVM IR to SDISel conversion. Is AA actually being recomputed using LLVM IR during codegen? > > In general, when AA is used during codegen, it grabs the IR value from the machine memoperands, then runs normal IR-level alias analysis. The IR needs to stay around and be immutable. That’...

On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > I have two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%u...

...lowing code snippet taken from StackColoring::remapInstructions clears a mem operand if it can't guarantee whether the memoperand's underlying value aliases with the merged allocas: // Update the MachineMemOperand to use the new alloca. 522 for (MachineInstr::mmo_iterator MM = I->memoperands_begin(), .... // Climb up and find the original alloca. 532 V = GetUnderlyingObject(V); 533 // If we did not find one, or if the one that we found is not in our 534 // map, then move on. 535 if (!V || !isa<AllocaInst>(V)) { 536 // Clear...

...u're looking for a property of an instruction, not an >> operand. If you're looking for vector instructions, that should be >> captured in TargetInstrInfo, not in MachineInstrs/Operands. > > Yes, I've written all that support. But that doesn't cover > MachineMemOperands. AFAIK there's no machine-independent way to tell which > instruction operands make up a MachineMemOperand. And even then, that would > only tell you about the compoenents that make up the address, not the data > itself. Note that having a machine-independent way to associate >...

On Jan 4, 2011, at 11:08 AM, Villmow, Micah wrote: > So, my question is, should isIdenticalTo take the memoperands into account? Is my patch correct? I almost feel like isIdenticalTo needs to be added to MachineMemOperand class. The MachineMemOperands are supposed to be used for optimizations only, your code should still be correct when stripping all memory operands. I think you would be better off encoding t...

On Thursday 03 April 2008 22:00:34 Dan Gohman wrote: > However, for people just interested in post-regalloc scheduling and > VLIW packing and similar things, MemOperands aren't the only approach. > A potentially better way to do this would be to extend MachineInstrs > to preserve the chain dependencies from the SelectionDAG. the selection dag may already contain unnecessary dependencies, even with alias analysis turned on. it is built after codegenprepa...

This seems to be what I am looking for. That was very helpful. Thank you. Erdem From: vlknkls at gmail.com Date: Wed, 16 Sep 2015 16:25:29 +0000 Subject: Re: [llvm-dev] How to add NOP? To: erdemderebasoglu at hotmail.com; llvm-dev at lists.llvm.org Use MachineInstr::memoperands() function to get memory operands then you can get the address space by using MachineMemOperand::getAddrSpace(). Volkan On Tue, Sep 15, 2015 at 11:40 PM Erdem Derebaşoğlu <erdemderebasoglu at hotmail.com> wrote: Thanks for the response. How can I find out if an instruction uses a private...

...analysis and -combiner-global-alias-analysis options. They basically work, though they aren't turned on by default currently. The algorithm used wants some scrutiny as well. * MachineInstrs currently don't reliably record information about memory accesses. This is being addressed by MemOperands. However, currently there is a problem; the current code misses memory references in anonymous patterns, like this in x86: def : Pat<(zextloadi64i32 addr:$src), (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), x86_subreg_32bit)>; I can provide more details about what's going on...

...> It sounds like you're looking for a property of an instruction, not an > operand. If you're looking for vector instructions, that should be > captured in TargetInstrInfo, not in MachineInstrs/Operands. Yes, I've written all that support. But that doesn't cover MachineMemOperands. AFAIK there's no machine-independent way to tell which instruction operands make up a MachineMemOperand. And even then, that would only tell you about the compoenents that make up the address, not the data itself. Note that having a machine-independent way to associate MachineOperands with...

On Jul 10, 2009, at 3:05 PM, David Greene wrote: > Here's the first of several patches to get comments into asm > output. This one > adds comment information to MachineInstructions and outputs it in the > generated AsmPrinters. This includes TableGen work to trigger the > comment > output in the right places. A couple of things are important to discuss: +

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def...