Displaying 3 results from an estimated 3 matches for "memop4".
Did you mean:
memop
2012 Nov 08
2
[LLVMdev] X86 Tablegen Description and VEX.W
Hi,
A question from r162999 changes:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999
For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and
"MemOp4" like those of "rm" or "rr" ?
multiclass fma4s< >
...
def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}&quo...
2012 Nov 08
0
[LLVMdev] X86 Tablegen Description and VEX.W
On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati
<anitha.boyapati at gmail.com>wrote:
...
> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and
> "MemOp4" like those of "rm" or "rr" ?
>
Hey Anitha,
The VEX.W bit is used to denote operand order. In other words, this bit
allows for a memop to be used as either the second or third source operand
of an FMA instruction, offering greater flexibility.
To conceptualize:
VFMAD...
2012 Nov 08
2
[LLVMdev] X86 Tablegen Description and VEX.W
...n McInally <cameron.mcinally at nyu.edu> wrote:
> On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>
> wrote:
> ...
>>
>> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and
>> "MemOp4" like those of "rm" or "rr" ?
>
>
> Hey Anitha,
>
> The VEX.W bit is used to denote operand order. In other words, this bit
> allows for a memop to be used as either the second or third source operand
> of an FMA instruction, offering greater flexibilit...