Displaying 9 results from an estimated 9 matches for "memhx".
2017 Feb 15
5
Unsigned int displaying as negative
...srcAReg, RegisterClass srcBReg,
>> RegisterClass dstReg, ValueType srcAType, ValueType
>> srcBType, ValueType dstType,
>> Operand ImmOd, ImmLeaf imm_type>
>> {
>> ....
>> def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx,
>> [(directStore (dstType (OpNode
>> imm_type:$srcA, (srcBType (load addr16:$srcB)))), addr16:$dstD)]>;
>> .....
>> }
>>
>> class SetABDIn<string asmstr, DAGOperand srcA, DAGOperand srcB,
>> DAGOperand
&g...
2017 Feb 15
4
Unsigned int displaying as negative
...tring asmstr, SDPatternOperator OpNode,
RegisterClass srcAReg, RegisterClass srcBReg,
RegisterClass dstReg, ValueType srcAType, ValueType
srcBType, ValueType dstType,
Operand ImmOd, ImmLeaf imm_type>
{
....
def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx,
[(directStore (dstType (OpNode
imm_type:$srcA, (srcBType (load addr16:$srcB)))), addr16:$dstD)]>;
.....
}
class SetABDIn<string asmstr, DAGOperand srcA, DAGOperand srcB, DAGOperand
dstD, list<dag> pattern>
: A_B_D<(outs), (...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...etADInOut<asmstr, srcAReg, dstReg,
[(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>;
def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
[(set dstReg:$dstD, (OpNode
imm_type:$srcA))]>;
def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
[(directStore (dstType (OpNode
imm_type:$srcA)), addr16:$dstD)]>;
def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
[(set dstReg:$dstD, (OpNode (srcAType (load
addr16:$srcA))))]>;
def REG_MEM : SetADIn<asmstr, srcAReg,...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...dstReg,
> [(set dstReg:$dstD, (OpNode
> srcAReg:$srcA))]>;
> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
> [(set dstReg:$dstD, (OpNode
> imm_type:$srcA))]>;
> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
> [(directStore (dstType (OpNode
> imm_type:$srcA)), addr16:$dstD)]>;
> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
> [(set dstReg:$dstD, (OpNode (srcAType (load
> addr16:$srcA))))]>;
> def REG_MEM...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(set dstReg:$dstD, (OpNode
>> srcAReg:$srcA))]>;
>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
>> [(set dstReg:$dstD, (OpNode
>> imm_type:$srcA))]>;
>> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
>> [(directStore (dstType (OpNode
>> imm_type:$srcA)), addr16:$dstD)]>;
>> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
>> [(set dstReg:$dstD, (OpNode (srcAType (load
>> addr16:$srcA))))]>;
&...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(set dstReg:$dstD, (OpNode
>>> srcAReg:$srcA))]>;
>>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
>>> [(set dstReg:$dstD, (OpNode
>>> imm_type:$srcA))]>;
>>> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
>>> [(directStore (dstType (OpNode
>>> imm_type:$srcA)), addr16:$dstD)]>;
>>> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
>>> [(set dstReg:$dstD, (OpNode (srcAType
>>> (load addr...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...D, (OpNode
>>>> srcAReg:$srcA))]>;
>>>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
>>>> [(set dstReg:$dstD, (OpNode
>>>> imm_type:$srcA))]>;
>>>> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
>>>> [(directStore (dstType (OpNode
>>>> imm_type:$srcA)), addr16:$dstD)]>;
>>>> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
>>>> [(set dstReg:$dstD, (OpNode (srcAType
>>...
2017 Feb 15
2
Unsigned int displaying as negative
Thanks for your reply.
We are propagating sign info to tablegen currently using
BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm.
I imagine (I have not looked) they are printed according to instruction in
AsmPrinter.cpp (pure speculation).
I'm still confused as to why 0x7FFF is ok to match 16 bit int but not
0x8000?
Thanks.
On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan,
> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Quentin,
>
> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:
>
> const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());
> VReg = MRI->createVirtualRegister(RC);
>
> My question is why is it using the