Displaying 6 results from an estimated 6 matches for "mem_reg".
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mem2reg
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...t;;
def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
[(set dstReg:$dstD, (OpNode
imm_type:$srcA))]>;
def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
[(directStore (dstType (OpNode
imm_type:$srcA)), addr16:$dstD)]>;
def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
[(set dstReg:$dstD, (OpNode (srcAType (load
addr16:$srcA))))]>;
def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
[(directStore (dstType (OpNode
srcAReg:$srcA)), addr16:$dstD)]>;
def ME...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...Out<asmstr, ImmOd, dstReg,
> [(set dstReg:$dstD, (OpNode
> imm_type:$srcA))]>;
> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
> [(directStore (dstType (OpNode
> imm_type:$srcA)), addr16:$dstD)]>;
> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
> [(set dstReg:$dstD, (OpNode (srcAType (load
> addr16:$srcA))))]>;
> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
> [(directStore (dstType (OpNode
> srcAReg:$srcA)), addr1...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...tReg,
>> [(set dstReg:$dstD, (OpNode
>> imm_type:$srcA))]>;
>> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
>> [(directStore (dstType (OpNode
>> imm_type:$srcA)), addr16:$dstD)]>;
>> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
>> [(set dstReg:$dstD, (OpNode (srcAType (load
>> addr16:$srcA))))]>;
>> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
>> [(directStore (dstType (OpNode
>> sr...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(set dstReg:$dstD, (OpNode
>>> imm_type:$srcA))]>;
>>> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
>>> [(directStore (dstType (OpNode
>>> imm_type:$srcA)), addr16:$dstD)]>;
>>> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
>>> [(set dstReg:$dstD, (OpNode (srcAType
>>> (load addr16:$srcA))))]>;
>>> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
>>> [(directStore (dstType (Op...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(set dstReg:$dstD, (OpNode
>>>> imm_type:$srcA))]>;
>>>> def IMM_MEM : SetADIn<asmstr, ImmOd, memhx,
>>>> [(directStore (dstType (OpNode
>>>> imm_type:$srcA)), addr16:$dstD)]>;
>>>> def MEM_REG : SetADInOut<asmstr, memhx, dstReg,
>>>> [(set dstReg:$dstD, (OpNode (srcAType
>>>> (load addr16:$srcA))))]>;
>>>> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
>>>> [(directSt...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan,
> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Quentin,
>
> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:
>
> const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());
> VReg = MRI->createVirtualRegister(RC);
>
> My question is why is it using the