Displaying 6 results from an estimated 6 matches for "mem_mem".
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2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...EG : SetADInOut<asmstr, memhx, dstReg,
[(set dstReg:$dstD, (OpNode (srcAType (load
addr16:$srcA))))]>;
def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
[(directStore (dstType (OpNode
srcAReg:$srcA)), addr16:$dstD)]>;
def MEM_MEM : SetADIn<asmstr, memhx, memhx,
[(directStore (dstType (OpNode (srcAType
(load addr16:$srcA)))), addr16:$dstD)]>;
}
defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs,
i16, i16, simm16, immSExt16x>;
On Tue, Aug 25, 2015 at...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...mhx, dstReg,
> [(set dstReg:$dstD, (OpNode (srcAType (load
> addr16:$srcA))))]>;
> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
> [(directStore (dstType (OpNode
> srcAReg:$srcA)), addr16:$dstD)]>;
> def MEM_MEM : SetADIn<asmstr, memhx, memhx,
> [(directStore (dstType (OpNode (srcAType
> (load addr16:$srcA)))), addr16:$dstD)]>;
> }
>
> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs,
> i16, i16, simm16, immSExt16x&g...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(set dstReg:$dstD, (OpNode (srcAType (load
>> addr16:$srcA))))]>;
>> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
>> [(directStore (dstType (OpNode
>> srcAReg:$srcA)), addr16:$dstD)]>;
>> def MEM_MEM : SetADIn<asmstr, memhx, memhx,
>> [(directStore (dstType (OpNode (srcAType
>> (load addr16:$srcA)))), addr16:$dstD)]>;
>> }
>>
>> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs,
>> i16, i...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(set dstReg:$dstD, (OpNode (srcAType
>>> (load addr16:$srcA))))]>;
>>> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
>>> [(directStore (dstType (OpNode
>>> srcAReg:$srcA)), addr16:$dstD)]>;
>>> def MEM_MEM : SetADIn<asmstr, memhx, memhx,
>>> [(directStore (dstType (OpNode (srcAType
>>> (load addr16:$srcA)))), addr16:$dstD)]>;
>>> }
>>>
>>> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseR...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...:$dstD, (OpNode (srcAType
>>>> (load addr16:$srcA))))]>;
>>>> def REG_MEM : SetADIn<asmstr, srcAReg, memhx,
>>>> [(directStore (dstType (OpNode
>>>> srcAReg:$srcA)), addr16:$dstD)]>;
>>>> def MEM_MEM : SetADIn<asmstr, memhx, memhx,
>>>> [(directStore (dstType (OpNode (srcAType
>>>> (load addr16:$srcA)))), addr16:$dstD)]>;
>>>> }
>>>>
>>>> defm MOV16Copy_ : AD<"mov16", null_frag, G...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan,
> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Quentin,
>
> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:
>
> const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());
> VReg = MRI->createVirtualRegister(RC);
>
> My question is why is it using the