Displaying 6 results from an estimated 6 matches for "mem_frag".
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mem_flags
2012 Nov 08
2
[LLVMdev] X86 Tablegen Description and VEX.W
...ot; ?
multiclass fma4s< >
...
def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>;
...
It seems that previous revisions for fma4 intrinsics also followed
similar trend. Any idea why?
--
Anitha
2012 Nov 16
2
[LLVMdev] Operand order in dag pattern matching in td files
...yway. I am using a pattern from
X86InstrFMA.td in the below example. Consider FMA3 pattern
(simplified).
let Constraints = "$src1 = $dst" in {
multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
SDPatternOperator OpNode = null_frag> {
def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}")...
2012 Nov 08
0
[LLVMdev] X86 Tablegen Description and VEX.W
On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati
<anitha.boyapati at gmail.com>wrote:
...
> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and
> "MemOp4" like those of "rm" or "rr" ?
>
Hey Anitha,
The VEX.W bit is used to denote operand order. In other words, this bit
allows for a memop to be used as
2012 Nov 16
1
[LLVMdev] Operand order in dag pattern matching in td files
...tern to be dropped.
Now having covered that the reason the operands are in the order they are
is because the only instruction that doesn't use null_frag is this one
defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)),
x86memop, RC, OpVT, mem_frag, OpNode>
Which specifies the operand order as 213 thus why they are 2, 1, 3 in the
pattern.
~Craig
On Fri, Nov 16, 2012 at 12:19 AM, Anitha B Gollamudi <
anitha.boyapati at gmail.com> wrote:
> On 16 November 2012 13:41, Anitha B Gollamudi <anitha.boyapati at gmail.com>
> wr...
2012 Nov 16
0
[LLVMdev] Operand order in dag pattern matching in td files
...om
> X86InstrFMA.td in the below example. Consider FMA3 pattern
> (simplified).
>
> let Constraints = "$src1 = $dst" in {
> multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
> RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
> SDPatternOperator OpNode = null_frag> {
>
> def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
> (ins RC:$src1, RC:$src2, RC:$src3),
> !strconcat(OpcodeStr,
> "\t{$src3, $src2, $d...
2012 Nov 08
2
[LLVMdev] X86 Tablegen Description and VEX.W
...to FMA4 class?
[3]. Why does only "rr" and "rm" forms have vex_w but not "mr" ?
(Reference)
multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
PatFrag mem_frag> {
def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst,
(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3...