Displaying 13 results from an estimated 13 matches for "mem2".
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2011 Nov 21
0
In-place modification of a matrix
...print(paste("Mem1", memory.size()))
for (i in 1:30) {
eval(parse(text="temp <- matrix1[10,]"))
eval(parse(text="matrix1[10,] <- temp * 0"))
}
print(paste("Mem2", memory.size()))
}))
print (paste("Time:", system.time(funcExample())[1], "secs"))
if (sum(matrix1) == 11999800) { print ("OK") } else { print ("NOT
OK") }
}
main()
[1] "OK"
[1] "Mem1 99.32"
[1] "Mem2...
2017 Jan 02
2
RFC: Allowing @llvm.objectsize to be more conservative with null.
...else.
I meant to say that it looks like the semantics of ObjectSizeMin(X) is
that "return the conservative minimum object size for all values that
X may take at runtime" (resp. ObjectSizeMax(X)).
For instance this:
void i(int c, volatile int* sink) {
void* mem1 = malloc(20);
void* mem2 = malloc(40);
*sink = __builtin_object_size(c ? mem1 : mem2, 0);
*sink = __builtin_object_size(c ? mem1 : mem2, 2);
}
is lowered to
movl $40, (%rsi)
movl $20, (%rsi)
ret
by GCC.
Applying the same logic to malloc(N), since it returns a location that
has N deref...
2007 Dec 02
2
Optimised qmf_synth and iir_mem16
...spx_word16_t *x1,
@ const spx_word16_t *x2,
@ const spx_word16_t *a,
@ spx_word16_t *y,
@ int N,
@ int M,
@ spx_word32_t *mem1,
@ spx_word32_t *mem2,
@ char *stack)
.global qmf_synth
qmf_synth:
stmdb sp!, { r4-r11, lr }
add r7, sp, #36 @ r0 = x1, r1 = x2, r2 = a, r3 = y
ldmia r7, { r4-r7 } @ r4 = N, r5 = M, r6 = mem1, r7 = mem2
add r8, r4, r5
sub r9, sp,...
2013 May 09
0
[LLVMdev] Predicated Vector Operations
...it. What we need is predication at
> the expression tree leaves, which is why we're talking about loads and
> stores. For loads, there is no %oldvalue so we don't have to worry
> about it.
>
> %ra = ...
> if (%mask) {
> %rb = [mem1]
> }
> else {
> %rb = [mem2]
> }
> %rc = %ra + %rb
>
> Would be translated to:
>
> %ra = ...
>
> %rt = load [mem1], %mask
> %rf = load [mem2], ~%mask
>
> %rb = select %mask, %rt, %rf
> %rc = fadd %ra, %rb
>
> Since the input select defined all vector elements we don't need selects...
2008 Jul 17
2
[LLVMdev] Casting between address spaces and address space semantics
...in which memory the array should be
allocated. This allows the backend to map the load and store instructions from
and to this array on the right target instructions, depending on the memory
used. For example:
__attribute__((address_space(1))) char mem1[100];
__attribute__((address_space(2))) char mem2[100];
Now, we are using a function which reads a value from one of these memories
and does some processing. Since we want to execute this function for multiple
memories, we make it accept a pointer in the generic address space (ie, no
address space attribute):
void do_stuff(char* mem);
Somewhe...
2013 Feb 27
0
[LLVMdev] Question about intrinsic function llvm.objectsize
...-----------------------
struct { T1* p1, T2 *p2, int xyz} mydata;
addr1 = phi(&mydata, &mydata); // all operands have same value.
addr2 = phi(&mydata.xyz, &mydata.xyz);
memcpy(addr1, ... sizeof(mydata)) // mem1
= load addr2->syz // mem2
--------------------------------------------------------
( But for the phi node, getUnderlyingObject() would return "mydata" as
"object" for both memory accesses. )
getObjectSize(mem2) return 4 instead of sizeof(mydata). Now that the
"object" only have 4 bytes,...
2013 Feb 27
2
[LLVMdev] Question about intrinsic function llvm.objectsize
...gt; struct { T1* p1, T2 *p2, int xyz} mydata;
>
> addr1 = phi(&mydata, &mydata); // all operands have same value.
> addr2 = phi(&mydata.xyz, &mydata.xyz);
>
> memcpy(addr1, ... sizeof(mydata)) // mem1
> = load addr2->syz // mem2
> --------------------------------------------------------
>
> ( But for the phi node, getUnderlyingObject() would return "mydata" as "object" for both memory accesses. )
> getObjectSize(mem2) return 4 instead of sizeof(mydata). Now that the "object" only...
2013 May 07
6
[LLVMdev] Predicated Vector Operations
I'm trying to understand how predicated/masked instructions can be
generated in llvm, specifically an instruction where a set bit in the mask
will write the new result into the corresponding vector lane in the
destination and a clear bit will cause the lane in the destination to
remain what it was before the instruction executed.
I've seen a few places that suggest 'select' is the
2017 Jan 02
2
RFC: Allowing @llvm.objectsize to be more conservative with null.
Hi George,
Have you considered changing our existing behavior to match GCC's
builtin_object_size instead of adding a new parameter? That may be
simpler overall. There's also a clear upgrade strategy -- fold every
old style call to "<min> ? 0 : 1".
You probably already know this, but GCC folds
builtin_object_size(0, 0) to -1 and builtin_object_size(0, 2) to 0.
We'll
2013 Feb 27
4
[LLVMdev] Question about intrinsic function llvm.objectsize
On Feb 27, 2013, at 4:05 AM, Nuno Lopes <nunoplopes at sapo.pt> wrote:
> Hi,
>
> Regarding the definition of object for @llvm.objectsize, it is identical to gcc's __builtin_object_size(). So it's not wrong; it's just the way it was defined to be.
>
> Regarding the BasicAA's usage of these functions, I'm unsure. It seems to me that isObjectSmallerThan()
2013 Feb 27
0
[LLVMdev] Question about intrinsic function llvm.objectsize
...2, int xyz} mydata;
>>
>> addr1 = phi(&mydata, &mydata); // all operands have same value.
>> addr2 = phi(&mydata.xyz, &mydata.xyz);
>>
>> memcpy(addr1, ... sizeof(mydata)) // mem1
>> = load addr2->syz // mem2
>> --------------------------------------------------------
>>
>> ( But for the phi node, getUnderlyingObject() would return "mydata" as "object" for both memory accesses. )
>> getObjectSize(mem2) return 4 instead of sizeof(mydata). Now that the "o...
2004 Sep 28
20
Polycom IP500
Got my first round of IP500s in today. Anybody have any example sip.cfg
files they'd like to share?
Tim Jackson
Network Engineer
Angelina County, Texas
(936)639-4827 office
(936)414-6723 mobile
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2012 Jun 24
0
nouveau _BIOS method
...p..ASLC.....h.
7a60: 70 69 41 4c 53 49 70 01 41 53 4c 43 a1 03 a4 01 piALSIp.ASLC....
7a70: 70 01 41 53 4c 45 a4 00 14 17 53 43 49 50 00 a0 p.ASLE....SCIP..
7a80: 0e 92 93 4f 56 45 52 00 a4 92 47 53 4d 49 a4 00 ...OVER...GSMI..
7a90: 5b 82 4e 04 5e 5e 4d 45 4d 32 08 5f 48 49 44 0c [.N.^^MEM2._HID.
7aa0: 41 d0 0c 01 08 5f 55 49 44 0a 02 08 43 52 53 5f A...._UID...CRS_
7ab0: 11 1d 0a 1a 86 09 00 01 00 00 00 20 00 00 20 00 ........... .. .
7ac0: 86 09 00 01 00 00 00 40 00 00 20 00 79 00 14 11 ....... at .. .y...
7ad0: 5f 43 52 53 00 a0 0a 49 47 44 53 a4 43 52 53 5f _CRS...IGDS...