Displaying 5 results from an estimated 5 matches for "mdmx".
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mdbx
2013 Nov 15
2
[LLVMdev] [PATCH] Add a Scalarize pass
...which is often a good example when it comes to complicated possibilities :-)).
It has at least four separate vector extensions:
- <2 x float> support from the MIPS V floating-point extensions,
carried over to MIPS 32/64.
- <8 x i8> and <4 x i16> support from the optional MDMX extension,
now deprecated but used on older chips like the SB-1 and (in a
modified form) the VR5400.
- Processor-specific vector extensions for the Loongson range.
- The new MSA ASE.
That's a lot of possiblities. Maybe the LLVM port will never support
Loongson and MDMX (almost c...
2013 Nov 15
0
[LLVMdev] [PATCH] Add a Scalarize pass
...le when it comes to complicated possibilities :-)).
> It has at least four separate vector extensions:
>
> - <2 x float> support from the MIPS V floating-point extensions,
> carried over to MIPS 32/64.
>
> - <8 x i8> and <4 x i16> support from the optional MDMX extension,
> now deprecated but used on older chips like the SB-1 and (in a
> modified form) the VR5400.
>
> - Processor-specific vector extensions for the Loongson range.
>
> - The new MSA ASE.
>
> That's a lot of possiblities. Maybe the LLVM port will never...
2013 Nov 14
0
[LLVMdev] [PATCH] Add a Scalarize pass
On Nov 14, 2013, at 2:32 PM, Richard Sandiford <rsandifo at linux.vnet.ibm.com> wrote:
> Richard Sandiford <rsandifo at linux.vnet.ibm.com> writes:
>> Are you worried that adding it to PMB will increase compile time?
>> The pass exits very early for any target that doesn't opt-in to doing
>> scalarisation at the IR level, without even looking at the function.
2013 Nov 14
2
[LLVMdev] [PATCH] Add a Scalarize pass
Richard Sandiford <rsandifo at linux.vnet.ibm.com> writes:
> Are you worried that adding it to PMB will increase compile time?
> The pass exits very early for any target that doesn't opt-in to doing
> scalarisation at the IR level, without even looking at the function.
As an alternative, adding Scalarizer and InstCombine passes to
SystemZPassConfig::addIRPasses() would probably
2009 Oct 13
3
Proposal for replacing asm code with intrinsics
Hi,
I'm new to Theora and would like to propose several performance optimization using advanced instructions in x86 CPUs (SSE2-SSE4.2).
There are several source files in \x86 and \x86_vc which developed using inline assembler. However this cause several maintenance problems:
1) Need to sync gcc & msvc versions
2) Only 32bit environment is supported
3) No support for newer than MMX