search for: mcwritelatencyentry

...latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of resources like latencies with a scheduling class. Can I ask you something to modify on tablegen? I think that the 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying the WriteResources of each defintion as commented on code. As you know, tablegen sets the 'WriteResourceID' field of 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is referenced by a 'ReadAdvance'. If we always set t...

Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST: InstrItinClass; def ALU1: ProcResource<...

...resource conflicts per cycle. In order to support >> this with LLVM, I expected a per-operand list of resources like >> latencies with a scheduling class. >> >> Can I ask you something to modify on tablegen? I think that the >> 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying >> the WriteResources of each defintion as commented on code. As you >> know, tablegen sets the 'WriteResourceID' field of >> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is >> referenced by a '...

...to support >>>> this with LLVM, I expected a per-operand list of resources like >>>> latencies with a scheduling class. >>>> >>>> Can I ask you something to modify on tablegen? I think that the >>>> 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying >>>> the WriteResources of each defintion as commented on code. As you >>>> know, tablegen sets the 'WriteResourceID' field of >>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is >&g...

...er interprets the model, but it is really up to your custom strategy to implement the model. > I have attached a patch that adds the 'ResourceDelays' field in tablegen. Could you have a look at it? A couple possible issues are: > - 'Delay' is signed, since 'Cycles' in MCWriteLatencyEntry is also signed. Sure. > - When an instruction accesses the same resource multiple times, the uses are aggregated in SubtargetEmitter::GenSchedClassTables. I'm not sure how that would work if we add a 'Delay' field to MCWriteProcResEntry. Me neither. I suggest adding an assert to m...

...but it is really up to your custom strategy to implement the model. >> >>> I have attached a patch that adds the 'ResourceDelays' field in tablegen. Could you have a look at it? A couple possible issues are: >>> - 'Delay' is signed, since 'Cycles' in MCWriteLatencyEntry is also signed. >> >> Sure. >> >>> - When an instruction accesses the same resource multiple times, the uses are aggregated in SubtargetEmitter::GenSchedClassTables. I'm not sure how that would work if we add a 'Delay' field to MCWriteProcResEntry. >>...

hacker cling wrote: > Hello all, > I was playing with LLVM pass. I changed the > lib/Transforms/Hello/Hello.cpp 's content to be my own pass. Then I make > install the pass and use an example test1.c to see whether it works or > not. When I run example using the following command: > clang -emit-llvm test1.c -c -o test1.bc > opt -load

Hello all, I was playing with LLVM pass. I changed the lib/Transforms/Hello/Hello.cpp 's content to be my own pass. Then I make install the pass and use an example test1.c to see whether it works or not. When I run example using the following command: clang -emit-llvm test1.c -c -o test1.bc opt -load ../build_llvm/Debug+Asserts/lib/LLVMHello.so -hello < test1.bc > /dev/null It