Displaying 8 results from an estimated 8 matches for "mcsuperregiterator".
2012 Sep 10
0
[LLVMdev] Assert in LiveInterval update
...ave a one-to-one mapping with machine operands, regunit intervals have a many-to-many mapping with the operands. A single physreg operand can affect multiple regunit intervals, and a regunit interval can be affected by different (overlapping) physregs.
It is best to avoid the MCRegUnitRootIterator+MCSuperRegIterator combination because the set of super-registers can be quite large on ARM.
/jakob
2012 Sep 12
1
[LLVMdev] Assert in LiveInterval update
...685. I'm still looking into a couple
of errors, but I suspect that these are due to my build configuration,
rather than the patch.
Sergei - could you let me know if this fixes your issue? Thanks again for
all of your work tracking this down.
> It is best to avoid the MCRegUnitRootIterator+MCSuperRegIterator
> combination because the set of super-registers can be quite large on ARM.
>
Done. I've used TRI.hasRegUnit as suggested. Thanks for the advice!
Cheers,
Lang.
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2016 Jul 19
2
Check sub register relations in RA
Hi there,
In my register allocator, I was trying to get the parent of a register in
ARM.
That is:
D0 <-> S0, S1.
Given S0, how am I able to get D0?
Thanks,
Xiaochu
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2012 Sep 10
3
[LLVMdev] Assert in LiveInterval update
Hi Jakob,
I've got a good test case that I'm working on at the moment. I noticed
something odd though: Is '0' a valid register unit? I'm seeing a
LiveInterval with li->reg == 0 show up, which previously wasn't valid. We
have a few checks around the place to disregard the '0' physreg - could
these trigger on interaction with a '0' interval? That could
2012 Jun 01
0
[LLVMdev] Heads up: MCRegisterInfo register list functions going away
I am going to remove these functions from MCRegisterInfo:
getSubRegisters()
getSuperRegisters()
getOverlaps()
getAliasSet()
They have been replaced with iterator classes, also defined in MCRegisterInfo.h:
MCSubRegIterator
MCSuperRegIterator
MCRegAliasIterator
The tree has lots of examples of how to use all three.
/jakob
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...UI != UE; UI.skipInstruction()) {
const MachineInstr* MI = &*UI;
SlotIndex InstSlot =
LIS.getSlotIndexes()->getInstructionIndex(MI);
if (InstSlot > LastUse && InstSlot < OldIdx)
LastUse = InstSlot;
}
//for (MCSuperRegIterator Supers(Root, &TRI); Supers.isValid();
++Supers)
// I do not think we should be doing this here.
}
} else {
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Reg),
UE = MRI.use_nodbg_end();
UI != UE; UI.ski...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
Hi Lang,
Just one more quick question. in LiveIntervalAnalysis.cpp In
SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx)
Did you really mean to use
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Reg),
UE = MRI.use_nodbg_end();
UI != UE; UI.skipInstruction()) {}
Aren't we currently dealing with units,
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...tr* MI = &*UI;****
>
> SlotIndex InstSlot =
> LIS.getSlotIndexes()->getInstructionIndex(MI);****
>
> if (InstSlot > LastUse && InstSlot < OldIdx) ****
>
> LastUse = InstSlot;****
>
> }****
>
> //for (MCSuperRegIterator Supers(Root, &TRI); Supers.isValid();
> ++Supers) ****
>
> // I do not think we should be doing this here…****
>
> }****
>
> } else {****
>
> for (MachineRegisterInfo::use_nodbg_iterator****
>
> UI = MRI.use_nodbg_begin(Reg)...