search for: mcsubregiterator

Hi there, In my register allocator, I was trying to get the parent of a register in ARM. That is: D0 <-> S0, S1. Given S0, how am I able to get D0? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160719/3cc73e78/attachment.html>

I am going to remove these functions from MCRegisterInfo: getSubRegisters() getSuperRegisters() getOverlaps() getAliasSet() They have been replaced with iterator classes, also defined in MCRegisterInfo.h: MCSubRegIterator MCSuperRegIterator MCRegAliasIterator The tree has lots of examples of how to use all three. /jakob

Hi Sergei, Register units != sub registers. Register units are an abstraction to describe overlapping of registers effectively. You probably wanted to use MCSubRegIterator. On Thu, Aug 30, 2012 at 2:30 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Hello Jakob and everyone, > > I am observing an issue with MCRegUnitIterator in my back end, and trying > to reverse engineer some of the table gen magic around it, but if you or > someone re...

...Mailing List > Subject: Re: [LLVMdev] MC Register mapping question (MCRegUnitIterator > ) > > Hi Sergei, > > Register units != sub registers. > > Register units are an abstraction to describe overlapping of registers > effectively. > > You probably wanted to use MCSubRegIterator. > > > On Thu, Aug 30, 2012 at 2:30 PM, Sergei Larin <slarin at codeaurora.org> > wrote: > > Hello Jakob and everyone, > > > > I am observing an issue with MCRegUnitIterator in my back end, and > > trying to reverse engineer some of the table gen magic...

Hello Jakob and everyone, I am observing an issue with MCRegUnitIterator in my back end, and trying to reverse engineer some of the table gen magic around it, but if you or someone readily knows the answer, I would highly appreciate it. Here is the problem. In my back end we have a rather simple int register file structure: // Integer registers. def R0 : Ri< 0, "r0">,

Andy, Lang, Thanks for the suggestion. I have spent more time with it today, and I do see some strange things in liveness update. I am not at the actual cause yet, but here is what I got so far: I have the following live ranges when I start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)...