Displaying 6 results from an estimated 6 matches for "mcstream".
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2014 Mar 12
2
[LLVMdev] Hazard recognition using MCInst
Dear All,
I am following a flow to generate object files(.o) from input (.s assembly) files.
The input .s is given to AsmParser, which creates MCInst after matching instruction opcode.
These MCInst are converted to MCStream and then finally emitting to an object file using Target Code Emitter.
I am considering whether hazard recognition can be done on the list of MCInst, which I get after parsing .s file ??
The hazard recognition available with LLVM, uses 'scheduling DAG of
Machine Instructions' and Alias A...
2016 Jun 12
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...st case to be testable in Release build too. Other minor
changes to adhere coding and naming conventions.
Testing:
======
test-suite has been tested with IPRA enabled.
Study and other:
=============
Learned about LNT, test-suite for LLVM, Inline assembly in LLVM IR, fastcc,
local functions, MCStream class. In C++ I leaned about emplace family of
methods in STL and perfect forwarding introduced in C++11.
Plan for next week:
1) Investigate issue related to functional correctness that leads to run
time failures
2) profile the compilation process to verify increase in time due to IPRA
3) Impr...
2016 Jun 15
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...adhere coding and naming conventions.
>
>
> Testing:
>
> ======
>
> test-suite has been tested with IPRA enabled.
>
>
> Study and other:
>
> =============
>
> Learned about LNT, test-suite for LLVM, Inline assembly in LLVM IR,
> fastcc, local functions, MCStream class. In C++ I leaned about emplace
> family of methods in STL and perfect forwarding introduced in C++11.
>
>
> Plan for next week:
>
> 1) Investigate issue related to functional correctness that leads to run
> time failures
>
> 2) profile the compilation process to ver...
2016 Jun 19
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...>>>
>>> test-suite has been tested with IPRA enabled.
>>>
>>>
>>> Study and other:
>>>
>>> =============
>>>
>>> Learned about LNT, test-suite for LLVM, Inline assembly in LLVM IR,
>>> fastcc, local functions, MCStream class. In C++ I leaned about emplace
>>> family of methods in STL and perfect forwarding introduced in C++11.
>>>
>>>
>>> Plan for next week:
>>>
>>> 1) Investigate issue related to functional correctness that leads to run
>>> time fail...
2016 Jun 20
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...nabled.
>>>>>
>>>>>
>>>>> Study and other:
>>>>>
>>>>> =============
>>>>>
>>>>> Learned about LNT, test-suite for LLVM, Inline assembly in LLVM IR,
>>>>> fastcc, local functions, MCStream class. In C++ I leaned about emplace
>>>>> family of methods in STL and perfect forwarding introduced in C++11.
>>>>>
>>>>>
>>>>> Plan for next week:
>>>>>
>>>>> 1) Investigate issue related to functional corr...
2016 May 28
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
Dear community,
This is to brief you the progress of Interprocedural Register Allocation,
for those who are interested to see the progress in terms of code please
consider http://reviews.llvm.org/D20769
This patch contains simple infrastructure to propagate register usage
information of callee to caller in call graph. The code generation order is
changed to follow bottom up order on call graph ,