search for: mcregunitrootiterator

...n with a '0' interval? That could introduce some subtle bugs. Right. Regunits are numbered independently from physregs, starting from 0. Each regunit corresponds to one or two physregs, the 'roots', which are typically leaf registers. The mapping is exposed by MCRegUnitIterator and MCRegUnitRootIterator. Regunit live intervals are more strictly defined than the old physreg intervals. The same way a virtreg interval can be computed from all machine operands mentioning the virtreg, regunit intervals can be computed from all physreg operands with TRI->hasRegUnit(MO.getReg(), RegUnit). However, w...

Hi Jakob, I've got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could these trigger on interaction with a '0' interval? That could

...tLastUseBefore in r163685. I'm still looking into a couple of errors, but I suspect that these are due to my build configuration, rather than the patch. Sergei - could you let me know if this fixes your issue? Thanks again for all of your work tracking this down. > It is best to avoid the MCRegUnitRootIterator+MCSuperRegIterator > combination because the set of super-registers can be quite large on ARM. > Done. I've used TRI.hasRegUnit as suggested. Thanks for the advice! Cheers, Lang. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pi...

...are so long. In most cases, it should be possible to express algorithms in terms of register units instead. I also want to avoid emitting tables for driving MCRegAliasIterator. If required, the set of aliasing registers can be computed from regunits and super-registers. (See the block comment for MCRegUnitRootIterator or LiveIntervals::computeRegUnitInterval). /jakob

...ng. In most cases, it should be possible to express algorithms in terms of register units instead. > > I also want to avoid emitting tables for driving MCRegAliasIterator. If required, the set of aliasing registers can be computed from regunits and super-registers. (See the block comment for MCRegUnitRootIterator or LiveIntervals::computeRegUnitInterval). > > /jakob > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...is. The findLastUseBefore() should probably look something like this: // Return the last use of reg between NewIdx and OldIdx. SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) { SlotIndex LastUse = NewIdx; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitRootIterator Roots(Reg, &TRI); Roots.isValid(); ++Roots) { unsigned Root = *Roots; for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Root), UE = MRI.use_nodbg_end(); UI != UE; UI.skipInstruction()) { const MachineInst...

Hi Lang, Just one more quick question. in LiveIntervalAnalysis.cpp In SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) Did you really mean to use for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg), UE = MRI.use_nodbg_end(); UI != UE; UI.skipInstruction()) {} Aren't we currently dealing with units,

...gt; > // Return the last use of reg between NewIdx and OldIdx.**** > > SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {**** > > SlotIndex LastUse = NewIdx;**** > > ** ** > > if (TargetRegisterInfo::isPhysicalRegister(Reg)) {**** > > for (MCRegUnitRootIterator Roots(Reg, &TRI); Roots.isValid(); > ++Roots) {**** > > unsigned Root = *Roots;**** > > for (MachineRegisterInfo::use_nodbg_iterator**** > > UI = MRI.use_nodbg_begin(Root),**** > > UE = MRI.use_nodbg_end();**** > >...