Displaying 6 results from an estimated 6 matches for "mcinstritineraries".
2015 Dec 04
2
InstrStage, Interpretation of getUnits()
Here is the code
<https://github.com/llvm-mirror/llvm/blob/c68dcdb413079d92118839dbd835e125293f411a/include/llvm/MC/MCInstrItineraries.h#L75>
for InstrStage::getUnits()
/// \brief Returns the choice of FUs.
unsigned getUnits() const { return Units_; }
This method returns an integer. How does one interpret it? As far as I see
it it should tell me what resources are used by a given stage but I can't
figure out what a return...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
...r example, one would expect that A and B should have the same value.But
> there is different API for accessing to A and B.
>
> An example of accessing to B in the source code can be found here:
> PPCInstrInfo::getInstrLatency. You can also look at getStageLatency in
> include/llvm/MC/MCInstrItineraries.h. From this two you can probably find
> other relevant places.
>
> Hope this helps
> Ehsan
>
>
> On Mon, Jun 6, 2016 at 2:37 PM, Phil Tomson via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> In our architecture loads from certain memory locations take...
2016 Jun 06
2
Instruction Itineraries: question about operand latencies
In our architecture loads from certain memory locations take a long time to
complete (on the order of 150 clock cycles). Since we don't have a way to
tell at compile time if the address being loaded from lies in slow or fast
memory, I've gone ahead and made all of the load numbers high, such as:
InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>,
However, I see that
2013 Apr 01
0
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
...eFunction *MF) {
+}
+
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index 7a2e47c..b201bd8 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -16,7 +16,9 @@
#include "MCTargetDesc/MipsReginfo.h"
#include "llvm/MC/MCInstrItineraries.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+
#include <string>
#define GET_SUBTARGETINFO_HEADER
@@ -25,6 +27,8 @@
namespace llvm {
class StringRef;
+class MipsTargetMachine;
+
class MipsSubtarget : public MipsGen...
2013 Apr 01
3
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote:
> IMHO the right way to handle target function attributes is to
> re-initialize the target machine and TTI for every function (if the
> attributes changed). Do you have another solution in mind ?
I don't really understand this.
TargetMachine and TTI may be quite expensive to initialize. Doing so for
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...tizer.h"
>> #include "llvm/CodeGen/MachineInstr.h"
>> #include "llvm/CodeGen/MachineInstrBundle.h"
>> -#include "llvm/CodeGen/ScheduleDAGInstrs.h"
>> #include "llvm/Target/TargetInstrInfo.h"
>> #include "llvm/MC/MCInstrItineraries.h"
>> using namespace llvm;
>> @@ -100,17 +100,17 @@ void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
>> reserveResources(&MID);
>> }
>>
>> -namespace {
>> +namespace llvm {
>> // DefaultVLIWScheduler - This class exte...