search for: mcinstlower

On Oct 18, 2011, at 2:46 PM, Jakob Stoklund Olesen wrote: > > On Oct 18, 2011, at 2:33 PM, Sanjoy Das wrote: > >>> it should be expanded late: In lib/Target/X86/X86MCInstLower.cpp. >> >> This is exactly what I was missing. Thanks a ton! :) > > We have three pseudo expansion passes: > > 1. ExpandISelPseudos.cpp - For instructions that may need to create basic blocks, like CMOV and atomics. > > 2. ExpandPostRAPseudos.cpp - For instruction...

> it should be expanded late: In lib/Target/X86/X86MCInstLower.cpp. This is exactly what I was missing. Thanks a ton! :) -- Sanjoy Das http://playingwithpointers.com

On Oct 18, 2011, at 2:33 PM, Sanjoy Das wrote: >> it should be expanded late: In lib/Target/X86/X86MCInstLower.cpp. > > This is exactly what I was missing. Thanks a ton! :) We have three pseudo expansion passes: 1. ExpandISelPseudos.cpp - For instructions that may need to create basic blocks, like CMOV and atomics. 2. ExpandPostRAPseudos.cpp - For instructions used to trick the register allocator...

Hi! The first patch fixes the problem of a MOV after a RET by emitting a fake instruction (as suggested by Duncan), which is lowered in MCInstLower. The second patch fixes a bug reported by -verify-machineinstrs. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Use-a-fake-instruction-for-the-stack-expansion-seque.patch Type: text/x-diff Size: 5276 b...

> > No problem. At some point the machine instructions represented by a class > "MachineInstr" are transformed into a representation using class "MCInst". > This is the MC level I'm talking about. It's the representation that the > llvm-mc uses. > > Do you mind pointing out where in the code this is happening? -- Rail Shafigulin Software

...M, MCStreamer &Streamer) > - : AsmPrinter(TM, Streamer) { } > + explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer); > > virtual bool runOnMachineFunction(MachineFunction &MF); > > @@ -38,6 +39,11 @@ > > /// Implemented in AMDGPUMCInstLower.cpp > virtual void EmitInstruction(const MachineInstr *MI); > + > +protected: > + bool DisasmEnabled; > + std::vector<std::string> DisasmLines, HexLines; > + size_t DisasmLineMaxLen; > }; > > } // End anonymous llvm > Index: lib/Target/R600/AMDGPUMCInst...

Hi, This patch adds R600/SI disassembly text to compiled object files, when a code dump is requested, to assist debugging in Mesa clients. Here's an example of the output in a Mesa client with a corresponding patch and RADEON_DUMP_SHADERS set: Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR6 ; BEFC0306

...ocumentation on the call sequence? I think I've reverse engineered it correctly, but I'm not completely sure.) - Introduced folding logic in foldMemoryOperand (analogous to PATCHPOINT, but which marks both load and store) -- this is where my problem currently lies - Inserted code during MCInstLower to record the statepoint The problem with this is that a reload from a stack slot will sometimes be inserted between the CALL and the SAFEPOINT. This is problematic since we are no longer recording the list of locations at the site of the call itself. If the recorded information is used durin...

Hi, I noticed a bunch of psuedo instructions used for creation of constants without generating loads. e.g. pxor xmm0, xmm0 Here is an example of what i am referring to snipped from X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; My question is

On 10/23/2011 03:24 AM, Sanjoy Das wrote: > Hi! > > The first patch fixes the problem of a MOV after a RET by emitting a > fake instruction (as suggested by Duncan), which is lowered in > MCInstLower. > > The second patch fixes a bug reported by -verify-machineinstrs. Do you want to add -verify-machineinstrs to the test? Your patch looks good to me. I will commit it tomorrow if no one objects. > Thanks! Thanks, Rafael

...nstant, with a PC-relative positive offset. Thus, the constant should be stored in .text section, after the load instruction, and offset should be computed at compile time (not link time). I struggle to find out : - how llvm handle constant pool - where I should compute the offset (MCCodeEmitter ? MCInstLowering ? ... ?) ARM has a specific pass for this (ARMConstantIslandPass.cpp), but I wonder if such a processing is really needed, at least for simple case (i.e. small enough offset). Handling this with relocations and linker-hacking seems odd, I'd prefer to avoid it. Thanks for you help, either wi...

Hi all, I'm trying to add a X86 pattern to turn movl $-1, %eax into orl $-1, $eax I can't find a way to express this in TableGen syntax though. def : Pat<(set GR32:$src, (i32 -1)), (OR32ri8 GR32:$src, -1)>; results in an assertion about 'Unknown Node'. Joerg

> From the department of ignorance and stupid suggestions: Run this > conversion after other passes that deal with call instructions? Yes, but my modifications are not made in a MachineFunctionPass, it's a custom inserter for an intrinsic... I'm not sure when intrinsic lowering is applied, but I guess before any MachineFunctionPass? So I'm not sure I can chosse the order at this