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I'm new to R so forgive me if this seems like a simple question: So I have table where the row titles are string variables. When I plot the data with rows along the x-axis, the data is ordered alphabetically as opposed to the order of the table. How can I preserve the row order of the table in the plot? Thanks in advance. -- View this message in context:

subscribe -------------------------------------------------------- Faerber Tobias Siemens AG ICM MP PD SW4 MCH 21 Information and Communication Mobile Grillparzerstrasse 10 a 81675 Munich, Germany Fixed net: +49 89 722 58578 Mobile net: +49 1755721351 Fax: +49 89 722 59070 <mailto:tobias.faerber@mch.siemens.de <mailto:tobias.faerber@mch.siemens.de> > -----------------------------------...

...hink this blogger pointed out some very good data. The reality of the age of the systems in comparison, as well as the "less than commodity" cluster configuration of the PC Servers. It too is also a "power hungry" setup, and very costly. The reality is that a dual-2.8GHz Xeon MCH system does _not_ have the same interconnect capable of an even _yesteryear_ UltraSPARC II hardware that actually had a _drastically_lower_ cost overall. And even then, for its age, price, etc..., the "old" 4-way UltraSPARC II NUMA/UPA was quite "competitive" against a processo...

Hello, Is there a list of software phones which will work with Asterisk? For Linux and Windows? I don't have any hardware yet, and before I buy anything I would like to know how Asterisk really works (with software "phones" for example). Tomek

Does anyone have any experience with Super-Micro brand motherboards // dual Xeon cpu's? Had to swap out my Tyan piece of junk and going back with the S-M board. I believe it has similar north/southbridge chips on it -- at least they are the intel MCH ICH5R and PXH plus the 82546GB. One area that the Tyan board was seriously lacking in was in the hardware monitoring department. The S-M board uses a winbond 83627HF chip. Another area I'm wondering about is with the SATA controller. Supposedly the ICH5R supports Raid 0, 1, and JBOD'...

>>Taddei Herve Com MD PD SWC 3 MCH 23 <herve.taddei@siemens.com><<< Wow!!! it seems that Siemens got an eye over speex ;-).... What other company is watching this closely at speex??? :-D just curious.... John Villar Gerente de Proyectos Computadores Flor Hard Soft 2058 C.A. www.florhard.com Taddei Herve Com MD PD...

.... Perhaps there are others as well. In section 39.6.2 "Winbind on Solaris 9" (p. 503), Solaris 9 users are directed to download a patch from the following URL: http://sunsolve.sun.com/pub-cgi/findPatch.pl?patchId=112960;rev=14 But the Sun site redirects users to a newer, longer, mch uglier URL: http://sunsolve.sun.com/search/advsearch.do?collection=PATCH&type=collec tions&max=50&language=en&queryKey5=112960;rev=14&toDocument=yes (Yeah, that's all one line.) I just thought I should mention it, in case there are other specific URLs for Sun web pag...

Dear gurus, Three DELL SC430s were purchased by my company a few months back and I've been told that when they spoke with the DELL representatives, they were informed that these servers were fully RHEL 4.0 compatible. Specs of the servers:- - Pentium 4 - 2.8 GHz - 1 GB RAM - 2x 250GB SATA HDDs I tried installing CentOS 4.0 on it but it doesn't seem to be able to detect any hard

...e it under certain conditions. See the GNU General Public Licence for details. As far as I can see all files are updated, so nothing is lost, but it is wasting bandwidth which is one of the great things about rsync! Anyone seen this before? Anyone know if there are fixes for it? Frank McNamara MCH Konsulting Sweden frank@abacus4.com _________________________________________________________________ Chat with friends online, try MSN Messenger: http://messenger.msn.com

...ust exchange pxelinux.0. I can reproduce the behaviour (Un)Fortunately, pxelinux 2.06 speeded up the TFTP download for a Gigabit line by nearly the factor 2. Therefore I really would love to use it... Any ideas what could cause the problem? TIA!! -- Bye, Gernot Hillier CT SE 2 Siemens AG, Mch P

...optind. The attached trivial patch resolves this problem for me and is also the suggested way to use getopt according to the man page. Therefore it should definitely not harm (also not for Linux) to include it in HEAD. TIA for applying this patch! -- Bye, Gernot Hillier CT SE 2 Siemens AG, Mch P

...ST_SHARE_MODES)? I'm doing ALL the necessary changes for my companies platforms in the Makefile only and am using a line FLAGSM = -DSVR4 -DSHADOW_PWD -DGUEST_SESSSETUP=1 -DFAST_SHARE_MODES -DALLOW_CHANGE_PASSWORD regards Stefan -- Stefan Kanthak e-mail: Stefan.Kanthak@mch.sni.de OEC BS2000 OS AP 2 'POSIX' WWW: http://D255S050.mch.sni.de/ Siemens Nixdorf Informationssysteme AG LAN-Manager: \\D255S050\PUBLIC\ Otto-Hahn-Ring 6 Telefon: +49 (89) 636-47598 81730 Muenchen Telefax: +49 (89) 63...

...ser 1. what's this? I use plain text passwords, and all the clients have the apropriate entries in the registry. thanks, dragos -- To unsubscribe from this list go to the following URL and read the instructions: http://lists.samba.org/mailman/listinfo/samba Return-Path: <ernst.sauerwein@mch.siemens.de> Delivered-To: samba@lists.samba.org Received: from david.siemens.de (david.siemens.de [192.35.17.14]) by lists.samba.org (Postfix) with ESMTP id 5DF7050D4 for <samba@lists.samba.org>; Thu, 9 Aug 2001 08:30:32 -0700 (PDT) X-Envelope-Sender-Is: ernst.sauerwein@mch.siemens.de...

...+ } else + cooked = xstrdup(raw); for (i = 0; mtab2[i].id != NULL; i++) { if (!strcmp(cooked, mtab2[i].id)) { @@ -74,7 +77,7 @@ static void guessmodel(const char *raw) char mch, *mstr; /* first see if it's in the mtab2 */ - if (check_mtab2(raw)) + if (check_mtab2(raw, 1)) return; mch = raw[17]; @@ -175,28 +178,36 @@ static char *get_id(void) void upsdrv_initinfo(void)...

I have made some changes to try and get the PDC working and now I am down to one thing where I believe the problem lies. All such documents on the setup show that the addition of users to the PDC should be added to passwd as well as LDAP but for my system that is not the case. I am running the listed software: Fedora Core 4 OpenLDAP 2.2.23 Samba 3.0.14a This is what currently happens when I

Hello, I have the same error, server is auto rebooted during every boot with kernel XEN, HS20 with Debian Wheezy and XEN hang on and AMM managment show same errors described in previous mails. With Debian wheezy wit non-xen kernel boots correcte, it seems that problems is with xen kernel Same Server HS20 with Debian Lenny+ XEN 3.2 or Debian Squeeze+XEN 4.0 working perfect Upgraded to Debian

In listening to this week''s Ruby on Rails Podcast the issue of YAML came up, and it got me thinking. Yes, YAML is very simple and cleanly defines both the database configuration and fixtures, but couldn''t the same thing be accomplished in Ruby? Jamis and others have encouraged the use of DSLs to simplify and clarify code. Since Django (whose author was on the podcast) uses

...s. Specifically, to my recollection, they used to use the TigerJet 320G, however somewhat recently, Tigerjet was bought out, and now the 320G is no longer produced. Maybe a better question is: is there a way I can take the latest DAHDI source and get a list of supported chipsets from it? Thanks. MCH -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.digium.com/pipermail/asterisk-users/attachments/20130402/26191e95/attachment.htm>

...users@lists.digium.com> > Message-ID: <004201c4d7b1$6101fd00$6400000a@work.makarios.us> > Content-Type: text/plain; format=flowed; charset="ISO-8859-2"; > reply-type=response > > > ----- Original Message ----- > From: "Tomasz Chmielewski" <mangoo@mch.one.pl> > To: "Asterisk Users Mailing List - Non-Commercial Discussion" > <asterisk-users@lists.digium.com> > Sent: Wednesday, December 01, 2004 4:42 AM > Subject: [Asterisk-Users] software phones for Asterisk - is there a > list? > > > > Hello, > &g...

...t for x86-64/PAE52, but it lacks many design considerations that the Athlon has -- especially outside the programmer/software considerations, and definitely more at the core interconnect/platform.. I.e., because Intel continues to use a single-point-of-contention "memory controller hub" (MCH), memory interconnect and I/O management, among other details, are still left to the MCH. This is going to become more and more of a headache. The reality is that the Intel IA-32e platform _must_ get past the "northbridge outside the CPU" attitude to compete with AMD. As such, I have _...