search for: mcg_cap

Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks than what the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that''s what we should use. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu...

Intercept guest reads of MSR_IA32_MCG_CAP and limit the number of memory banks reported to one. This prevents us from trying to read status of non-existent banks when migrated to a machine with fewer banks. Signed-off-by: Ben Guthro Signed-off-by: David Lively <dlively@virtualiron.com> ____________________________________________...

Hi, This is updated xen vMCE design foils, according to comments from community recently. This foils focus on vMCE part of Xen MCA, so as Keir said, it''s some dense. Later Will will present a document to elaborate more, including Intel MCA and surrounding features and Xen implementation. Thanks, Jinsong

...0000000,ffff0000 (XEN) run: [32767.30] pri=-64 flags=0 cpu=30 (XEN) CPU[31] sort=1108, sibling=00000000,00000000,00000000,c0000000, core=00000000,00000000,00000000,ffff0000 (XEN) run: [32767.31] pri=-64 flags=0 cpu=31 (XEN) irq.c:375: Dom1 callback via changed to Direct Vector 0xf3 (XEN) MCE: rd MCG_CAP 0x1000c02 (XEN) MCE: rd MCG_CAP 0x1000c02 (XEN) MCE: rd MCG_CAP 0x1000c02 (XEN) MCE: wr MC0_STATUS 0 (XEN) MCE: wr MC1_STATUS 0 (XEN) APIC error on CPU28: 00(40) (XEN) APIC error on CPU28: 40(40) (XEN) MCE: rd MCG_CAP 0x1000c02 (XEN) MCE: rd MCG_CAP 0x1000c02 (XEN) MCE: rd MCG_CAP 0x1000c02 (XEN) M...

Hi! The MCG_CAP MSR never returns a negative count of available error-reporting banks. Thus make nr_mce_banks unsigned. While here, do some other minor cleanups. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- AMD Saxony, Dresden, Germany Operating System Research Center Legal Information...

Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks that the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that''s what we should use. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu...

...ris, Here is the updated patch for determining number of regiter banks on AMD plus a patch removing shared_bank array, as you suggested. Offline/online testing didn''t show any issues. Boris Ostrovsky (2): x86/mce: Replace shared_bank array with is_shared_bank() helper x86/mce: Use MCG_CAP MSR to find out number of banks on AMD arch/x86/kernel/cpu/mcheck/mce_amd.c | 38 ++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 15 deletions(-) -- 1.8.1.2

This patch supports basic gfx passthrough on QEMU: - disable emulated VGA adpater if there is passthroughed gfx - register/unregister legacy VGA I/O ports and MMIOs for passthroughed gfx Signed-off-by: Ben Lin <ben.y.lin@intel.com> Signed-off-by: Weidong Han <weidong.han@intel.com> _______________________________________________ Xen-devel mailing list