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...let op = 1; let Inst{29-0} = disp; } The Uses=[O0,O1,O2,O3,O4,O5] is causing this crash (and similar crashes in the PQBP and Greedy allocators if I remember right). I fixed this in the MicroBlaze backend by remodeling the call instructions to be variadic like other backends. See the MBlazeInstrInfo.td changes in this commit: http://www.llvm.org/viewvc/llvm-project?view=rev&revision=121994 NOTE: In the commit R1 is the dedicated stack register on the MicroBlaze architecture. -- Wesley Peck University of Kansas SLDG Laboratory

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }

...g tblgen. Here is the error I got when modifying the MBlaze backend: BSLLI: (set CPURegs:i32:$dst, (shl:i32 CPURegs:i32:$b, (imm:{i32:v8i16})<<P:Predicate_immZExt5>>:$c)) ../../../bin/tblgen: error: Included from .../llvm/lib/Target/MBlaze/MBlaze.td:25: .../llvm/lib/Target/MBlaze/MBlazeInstrInfo.td:347:5: error: In BSLLI: Could not infer all types in pattern! def BSLLI : ArithI<0x11, "bslli ", shl, uimm5, immZExt5>; ^ It seems that defining a new register class changes how the tblgen infers the types in the DAG patterns. So what is the right way to add a registe...

Can someone explain how the condition code is passed from the MBlazeTargetLowering::LowerSELECT_CC to MBlazeTargetLowering::EmitCustomSelect custom inserter? In LowerSELECT_CC the condition code is never accessed (Op.GetOperand(4)) and I don't see how it ends up getting correctly passed to the MBlazeTargetLowering::EmitCustomSelect. > SDValue