Displaying 3 results from an estimated 3 matches for "mblaeschedul".
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mblaeschedule
2011 Aug 15
2
[LLVMdev] Question on instruction itineraries
...may be completely off.
I'm trying to model a CPU that has a latency of 2 cycles for multiplications
fully pipelined (so it can start a new one after one cycle)
First of all, is there a document that describes the instruction itinerary
model in some detail ?
For example looking at MBlaze target MBlaeSchedule.td I can see something
like
MblazeSchedule.td
...
def IIImul : InstrItinClass;
...
InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
has something similar.
In Mblaze case I...
2011 Aug 16
0
[LLVMdev] Question on instruction itineraries
...gt; I'm trying to model a CPU that has a latency of 2 cycles for multiplications
> fully pipelined (so it can start a new one after one cycle)
> First of all, is there a document that describes the instruction itinerary
> model in some detail ?
> For example looking at MBlaze target MBlaeSchedule.td I can see something
> like
> MblazeSchedule.td
> ...
> def IIImul : InstrItinClass;
> ...
> InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
>
> Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
>...
2011 Aug 17
1
[LLVMdev] Question on instruction itineraries
...CPU that has a latency of 2 cycles for
> multiplications
> > fully pipelined (so it can start a new one after one cycle)
> > First of all, is there a document that describes the instruction
> itinerary
> > model in some detail ?
> > For example looking at MBlaze target MBlaeSchedule.td I can see something
> > like
> > MblazeSchedule.td
> > ...
> > def IIImul : InstrItinClass;
> > ...
> > InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
> >
> > Does that mean Mul's are expected to hav...