search for: mbbi

This seems a very natural approach but I probably am having a trouble with the iterator invalidation. However, looking at other peephole optimizers passes, I couldn't see how to do this: #define BUILD_INS(opcode, new_reg, i) \ BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; ++MFI) { MachineBasicBlock* MBB = MFI; for (MachineBasicBlock::iterator MBBI = MBB->begin(); MB...

In many places there is code that looks like: MBBI = next(MBBI); In C++0X there is a std::next that is likely to be in scope when these calls are made. And due to ADL the above call becomes ambiguous: llvm::next or std::next? I recommend: MBBI = llvm::next(MBBI); -Howard

I made the change to the BuildMI() call. Again, I don't think that matters. #define BUILD_INS(opcode, new_reg, i) \ BuildMI(*MBB, OldMI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) I didn't completely understand your other proposed change: ​ for (MachineBasicBlock::iterator MBBI = MBB->begin(); MBBI != MBB->end(); ) { MachineInstr *NewMI = NULL; OldMI =...

Hi, I am writing an llvm pass wherein I require to iterate MachineBasicBlocks in reverse. The ilist reverse_iterator is not functioning as expected. Nor is the ilist iterator working in reverse (although -- operator is overloaded to do so). for (MachineFunction::iterator MBBI = mf_->end(), E = mf_->begin();MBBI != E; --MBBI) { MachineBasicBlock *MBB = MBBI; DEBUG(dbgs()<<*MBB<<"\n"); } Any suggestion would be helpful. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://l...

...er an operand came // before or after another operand. unsigned time; time = 0; // Initialize time. // For each block: for( MachineFunction::iterator mfi=Fn.begin(), mfe=Fn.end(); mfi != mfe; ++mfi ) { // for each byte code line: for( MachineBasicBlock::iterator mbbi = mfi->begin(), mbbe = mfi->end(); mbbi != mbbe; ++mbbi ) { // for each variable used: for( int opi=0, ope=mbbi->getNumOperands(); opi != ope; ++opi ) { // Get the variable const MachineOperand mop = mbbi->getOperand( opi );...

...eLowering.cpp (Arbeitskopie) @@ -323,11 +323,18 @@ } void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { + MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert((MBBI->getOpcode() == ARM::tBX_RET || - MBBI->getOpcode() == ARM::tPOP_RET) && - "Can only insert epilog into returning blocks"); + MBBI->getOpcode() == ARM::tPOP_RET || + MBBI->getOpcode() == A...

...nstruction. But I just don't think that's it. The creation of the new instruction works fine (works fine with OldMI as well) and the new instruction is present in the assembly output. The problem is removing the old instruction correctly. > The loop header needs to be modified, because MBBI will be invalidated when you remove the instruction: So if I remove the old instruction with something like: MBB->remove_instr(OldMI); I could just start the loop over or is there a more better way to invalidate the MBBI iterator? Basic blocks aren't that long (on average 4-6 instructio...

...iterating over the virtual registers - Check to see if the virtual register's "next" value exists outside of the basic block. for instance: std::vector<unsigned> findLiveOut( MachineBasicBlock * mbb ) { std::vector<unsigned> liveout; for( MachineBasicBlock::iterator mbbi = mbb->begin(), mbbe = mbb->end(); mbbi != mbbe; ++mbbi ) { for( opi = 0, ope = mbbi->getNumOperands(); opi < ope; ++opi ) { MachineOperand & operand = mbbi->getOperand(opi); if( operand.isReg() == false ) continue; if( operand.getReg() == 0 )...

On Nov 16, 2009, at 1:43 PM, Dale Johannesen wrote: > > On Nov 14, 2009, at 3:16 PMPST, Howard Hinnant wrote: > >> In many places there is code that looks like: >> >> MBBI = next(MBBI); >> >> In C++0X there is a std::next that is likely to be in scope when these >> calls are made. And due to ADL the above call becomes ambiguous: >> llvm::next or std::next? >> >> I recommend: >> >> MBBI = llvm::next(MBBI); >>...

...the basic block surgery of replacing the old MachineInst. The peephole pass gets called per MachineFunction and then iterates over each MachineBasicBlock and in turn over each MachineInst. When it finds an instruction which should be replaced, it builds a new instruction: NewMI = BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) .addReg(X86::new_reg, kill) .addImm(i); This works and it correctly places the new instruction just before the old instruction in the assembly output. So far so good. Now I have to remove the old instruction. But everything I try crashes...

On Nov 14, 2009, at 3:16 PMPST, Howard Hinnant wrote: > In many places there is code that looks like: > > MBBI = next(MBBI); > > In C++0X there is a std::next that is likely to be in scope when these > calls are made. And due to ADL the above call becomes ambiguous: > llvm::next or std::next? > > I recommend: > > MBBI = llvm::next(MBBI); > > -Howard "next" is a p...

On Nov 16, 2009, at 10:49 AMPST, Howard Hinnant wrote: > On Nov 16, 2009, at 1:43 PM, Dale Johannesen wrote: > >> >> On Nov 14, 2009, at 3:16 PMPST, Howard Hinnant wrote: >> >>> In many places there is code that looks like: >>> >>> MBBI = next(MBBI); >>> >>> In C++0X there is a std::next that is likely to be in scope when >>> these >>> calls are made. And due to ADL the above call becomes ambiguous: >>> llvm::next or std::next? >>> >>> I recommend: >>> >&...

...preciated - or any reference to an example, even better. [code is iterating through the MachineBasicBlock - this code is pretty straightforward and you can probably guess what's in it] if (Opcode == SP::FMULS) { MachineOperand& MO = MI.getOperand(0); DebugLoc DL = MBBI->getDebugLoc(); BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD), MO.getReg()); [ Then we'd do the second fstod and the fmuld, but I've not included this because the basic problem of generating the MachineInstr has happened already for this first MachineInstr] MI.eras...

...ious obscure reasons I'd like to detect the condition when X86 CALL instruction immediately precedes a function epilogue in the final emitted code, and insert a NOP between them if that happens. My initial attempt at it looked like this: MachineBasicBlock& MBB; MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would be inserted if (MBBI != MBB.begin() ? MBBI->getPrevNode()->isCall() : MBB.getPrevNode()->back().isCall()) { // insert NOP } However, this did not work because at the stage where I am trying to do this (in X86FrameLowering::emitEpilogue), th...

Is there an easy way to obtain all liveout variables of a basic block? Liveins can be found for each MachineBasicBlock, but I can only find liveouts for the whole function, at MachineRegisterInfo. Do I need to find them out manually?

On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > What I need to know is how to access the machine register classes. Also, I > need to know which virtual register is to be mapped into each specific > register class. I assume there is type information on the registers. I need > to know how to access it. MachineRegisterInfo::getRegClass will give you the TargetRegisterClass

...w. + if (! ShrinkWrapping) + return true; Why not just return inside if (allCSRUsesInEntryBlock)? 10. +bool PEI::calculateUsedAnticAvail(MachineFunction &Fn) { ... + // Calculate AnticIn, AnticOut using post-order traversal of MCFG. + for (po_iterator<MachineBasicBlock*> + MBBI = po_begin(Fn.getBlockNumbered(0)), + MBBE = po_end(Fn.getBlockNumbered(0)); MBBI != MBBE; ++MBBI) { + MachineBasicBlock* MBB = *MBBI; ... + // Calculate Avail{In,Out} via top-down walk of Machine dominator tree. + for (df_iterator<MachineDomTreeNode*> DI = df_begin(DT.getRootN...

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

Here is an updated patch for shrink wrapping with: - spills/restores done with stack slot stores/loads - stack adjustment removed - refactoring (but still in need of more) - spill/restore insertion code unified with spill/restore placement code Documentation available here<http://wiki.github.com/jdmdj/llvm-work/shrink-wrapping-work> illustrates shrink wrapping with loops and discusses a

Hi, while taking a look at X86PadShortFunction.cpp I found that /// addPadding - Add the given number of NOOP instructions to the function /// just prior to the return at MBBI void PadShortFunc::addPadding(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI, unsigned int NOOPsToAdd) { DebugLoc DL = MBBI->getDebugLoc(); while (NOOPsToAdd-- > 0) { BuildMI(*MBB, MBBI, DL, TII->get(X86::N...