search for: mbbe

...ual registers - Check to see if the virtual register's "next" value exists outside of the basic block. for instance: std::vector<unsigned> findLiveOut( MachineBasicBlock * mbb ) { std::vector<unsigned> liveout; for( MachineBasicBlock::iterator mbbi = mbb->begin(), mbbe = mbb->end(); mbbi != mbbe; ++mbbi ) { for( opi = 0, ope = mbbi->getNumOperands(); opi < ope; ++opi ) { MachineOperand & operand = mbbi->getOperand(opi); if( operand.isReg() == false ) continue; if( operand.getReg() == 0 ) continue; if( !...

...not just return inside if (allCSRUsesInEntryBlock)? 10. +bool PEI::calculateUsedAnticAvail(MachineFunction &Fn) { ... + // Calculate AnticIn, AnticOut using post-order traversal of MCFG. + for (po_iterator<MachineBasicBlock*> + MBBI = po_begin(Fn.getBlockNumbered(0)), + MBBE = po_end(Fn.getBlockNumbered(0)); MBBI != MBBE; ++MBBI) { + MachineBasicBlock* MBB = *MBBI; ... + // Calculate Avail{In,Out} via top-down walk of Machine dominator tree. + for (df_iterator<MachineDomTreeNode*> DI = df_begin(DT.getRootNode ()), + E = df_end(DT.getRootNode()); D...

Here is an updated patch for shrink wrapping with: - spills/restores done with stack slot stores/loads - stack adjustment removed - refactoring (but still in need of more) - spill/restore insertion code unified with spill/restore placement code Documentation available here<http://wiki.github.com/jdmdj/llvm-work/shrink-wrapping-work> illustrates shrink wrapping with loops and discusses a

Is there an easy way to obtain all liveout variables of a basic block? Liveins can be found for each MachineBasicBlock, but I can only find liveouts for the whole function, at MachineRegisterInfo. Do I need to find them out manually?

.../ before or after another operand. unsigned time; time = 0; // Initialize time. // For each block: for( MachineFunction::iterator mfi=Fn.begin(), mfe=Fn.end(); mfi != mfe; ++mfi ) { // for each byte code line: for( MachineBasicBlock::iterator mbbi = mfi->begin(), mbbe = mfi->end(); mbbi != mbbe; ++mbbi ) { // for each variable used: for( int opi=0, ope=mbbi->getNumOperands(); opi != ope; ++opi ) { // Get the variable const MachineOperand mop = mbbi->getOperand( opi ); // If it is a...

...nction do this rewrite? Specifically: // perform a final pass over the instructions and compute spill // weights, coalesce virtual registers and remove identity moves. const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { [...] for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { const MachineOperand &mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtua...

On Mon, Mar 2, 2009 at 10:35 AM, Evan Cheng <echeng at apple.com> wrote: > > On Mar 1, 2009, at 2:57 PM, John Mosby wrote: > > Obviously, all of this applies only when spills are done with push/pop, > which is the case on x86. I used this issue to start looking at generalizing > how spills and restores are handled, before looking too closely at other > targets, and

...t; 10. > +bool PEI::calculateUsedAnticAvail(MachineFunction &Fn) { > ... > + // Calculate AnticIn, AnticOut using post-order traversal of MCFG. > + for (po_iterator<MachineBasicBlock*> > > > + MBBI = po_begin(Fn.getBlockNumbered(0)), > > > + MBBE = po_end(Fn.getBlockNumbered(0)); MBBI != MBBE; ++MBBI) { > > > + MachineBasicBlock* MBB = *MBBI; > ... > + // Calculate Avail{In,Out} via top-down walk of Machine dominator tree. > > > + for (df_iterator<MachineDomTreeNode*> DI = df_begin(DT.getRootNode()), >...

...AnticAvail(MachineFunction &Fn) { >> ... >> +  // Calculate AnticIn, AnticOut using post-order traversal of MCFG. >> +  for (po_iterator<MachineBasicBlock*> >> >> >> +         MBBI = po_begin(Fn.getBlockNumbered(0)), >> >> >> +         MBBE = po_end(Fn.getBlockNumbered(0)); MBBI != MBBE; ++MBBI) { >> >> >> +    MachineBasicBlock* MBB = *MBBI; >> ... >> +  // Calculate Avail{In,Out} via top-down walk of Machine dominator tree. >> >> >> +  for (df_iterator<MachineDomTreeNode*> DI = d...

...Specifically: > > // perform a final pass over the instructions and compute spill > // weights, coalesce virtual registers and remove identity moves. > const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); > > for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); > mbbi != mbbe; ++mbbi) { > [...] > > for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { > const MachineOperand &mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && >...

On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > What I need to know is how to access the machine register classes. Also, I > need to know which virtual register is to be mapped into each specific > register class. I assume there is type information on the registers. I need > to know how to access it. MachineRegisterInfo::getRegClass will give you the TargetRegisterClass

...cifically: > > // perform a final pass over the instructions and compute spill > // weights, coalesce virtual registers and remove identity moves. > const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); > > for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_- > >end(); > mbbi != mbbe; ++mbbi) { > [...] > > for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { > const MachineOperand &mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() &&...

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

On Thu, 12 Apr 2007, David Greene wrote: > As I work toward improving LLVM register allocation, I've > come across the need to do some refactoring. cool. :) One request: Evan is currently out on vacation until Monday. This is an area that he is very interested in and will want to chime in on. Please don't start anything drastic until he gets back :). > Specifically, I would

Hi all, As I work toward improving LLVM register allocation, I've come across the need to do some refactoring. Specifically, I would like to separate register coalescing from live interval analysis. Right now LiveIntervals handles both. The reason I want to separate them is that other types of register allocators might like to do coalescing differently (e.g. graph coloring does it by

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

...gt; + // R0 = ... (Insn 2) >> + // Here, Insn 1 will result in the dependence graph not emitting an output >> + // dependence between Insn 0 and Insn 2. This can lead to incorrect >> + // packetization >> + // >> + for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); >> + MBB != MBBe; ++MBB) { >> + MachineBasicBlock::iterator End = MBB->end(); >> + MachineBasicBlock::iterator MI = MBB->begin(); >> + while (MI != End) { >> + if (MI->isKill()) { >> + MachineBasicBlock::iterator De...