search for: mbb1

...are the same _LDRrs_ instruction with the same operands. The problem is the call to _TTI->removeBranch(...)_ function that does not remove the _BX_ instruction. Thus, when removing the common instructions, the _BX_ is removed instead of the _LDRs_ instruction. > # Before removeBranch call on MBB1 > BB#9: derived from LLVM BB %if.else.i.i.i.i > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#7 > STRBi12 %R6, %R7<kill>, 0, pred:14, pred:%noreg; mem:ST1[%21](align=4) > %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred...

Can you please post the code to split a MachineBasicBlock? I am trying to split a MachineBasicBlock at a specific instruction in the MBB, let us say, into MBB1 and MBB2. This instruction should go into MBB2. Also MBB1 should have an unconditional branch to MBB2 as the terminator. (quite similar to splitBasicBlock in BasicBlock.cpp) Meanwhile, I am trying to come up with a variant of SplitCriticalEdge to do this but if someone can provide the code to spli...

...* instruction with the same operands. The > problem is the call to *TTI->removeBranch(...)* function that does not > remove the *BX* instruction. Thus, when removing the common instructions, > the *BX* is removed instead of the *LDRs* instruction. > > # Before removeBranch call on MBB1 > BB#9: derived from LLVM BB %if.else.i.i.i.i > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#7 > STRBi12 %R6, %R7<kill>, 0, pred:14, pred:%noreg; mem:ST1[%21](align=4) > %R6<def> = LDRrs %R4, %R6<kill>,...

> On 2015-Jun-04, at 12:45, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > >> On 2015-Jun-04, at 12:28, Ivan Baev <ibaev at codeaurora.org> wrote: >> >> Hi, we got the following assert: >> >> assert(!Working[0].isLoopHeader() && "entry block is a loop header"); >> >> [in

...after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will find R4 first is killed, then is used. It can not unlogisch. Attually R4 just is <Used>. It will cause my optimization pass crash(Actually, I ingore Live In message of MBB. I recollect live in messges at my pass.). 1. Does <kill> attribute of R4 at MBB0 is a unimpor...

Using 'NEW_BB->setIsLandingPad(true);' seems to resolve everything. Greetings, Jeroen Dobbelaere [...]

...CALL_R instruction and having a label to the new MBB: For following piece of code: --- typedef int callme_t(int a, int b); callme_t* c01; int foo(int a, int b) { return c01(a,b); // MachineBasicBlock will be split at call instruction } --- I have initially following correspondence: BB1 -> MBB10 (aka, BasicBlock 1 corresponds to MachineBasicBlock 10) After splitting MBB10 at the call instruction, we get : BB1 -> MBB10, MBB11 Because I need the address of MBB11, I found that I need to ensure that 'MBB11->hasAddressTaken()' returns true. Otherwise it can be optimized a...

...IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same thing. > R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will find R4 first is killed, then is used. It can not unlogisch. Attually R4 just is <Used>. It will cause my optimization pass crash(Actually, I ingore Live In message of MBB. I recollect live in messges at my pass.). A register should not be used after it is killed, and if it...

...me.cgi?name=CVE-2008-3530 The latest revision of this advisory is available at http://security.FreeBSD.org/advisories/FreeBSD-SA-08:09.icmp6.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (FreeBSD) iD8DBQFIvu2hFdaIBMps37IRAjxxAJwIIXP+ALAZkvG5m687PC+92BtXTwCfUZdS AvvrO0r+UAa6bn1H9mFf9So= =MBB1 -----END PGP SIGNATURE-----