search for: mayneedrelaxation

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to

Hi, I have kept working on this and found the following (as llvm 3.5): 1) In the function MCObjectStreamer::EmitInstruction there is a check for the instruction being relaxable or not: if (!Assembler.getBackend().mayNeedRelaxation(Inst)) { EmitInstToData(Inst, STI); return; } At this stage, the instruction as been already selected to be ARM::ADR. The call to mayNeed 2015-07-07 18:06 GMT+03:00 Tim Northover <t.p.northover at gmail.com>: > On 7 July 2015 at 06:06, Eric Bentura <ebentura at gmail.com&gt...

...ample here is the x86 jmp instruction: the choice between near and long jumps (and hence 2 bytes or 5 bytes on x86-64) is not made until the actual conversion to MCInst and after applying all of the fixups--which only happens deep within the bowels of the AsmPrinter pass. Right. See X86AsmBackend::mayNeedRelaxation() and friends for the gory details. -jim > > -- > Joshua Cranmer > News submodule owner > DXR coauthor > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiu...

On 10/23/2012 1:58 PM, John Criswell wrote: > Dear All, > > I'm enhancing a MachineFunctionPass that enforces control-flow > integrity. One of the things I want to do is to set the alignment of > an instruction (by adding NOPs before it in the MachineBasicBlock or > by emitting an alignment directive to the assembler) if it causes a > specific sequence of bytes to be

I have created a small ll file to reproduce the problem. I used the intrinsic function llvm.arm.space to introduce space between the beginning of the code and the jump table. If the first argument of llvm.arm.space is higher than INT_MAX ( *2147483647)*, then the bug is hit. Lower or equal to that value, it passes. It looks like a precision issue. Does this sound familiar to someone? ; ModuleID =

Hi all, In RISC-V ISA, the range of conditional branches is within 4KiB. In current implementation, if the branch target is out of range, LLVM MC will issue an error message to tell users it could not resolve the fixup record. I have compared the result with the GNU assembler. GNU assembler will convert the branch to inverted one plus jump to make the branch possible. The range of unconditional

Dear All, I'm enhancing a MachineFunctionPass that enforces control-flow integrity. One of the things I want to do is to set the alignment of an instruction (by adding NOPs before it in the MachineBasicBlock or by emitting an alignment directive to the assembler) if it causes a specific sequence of bytes to be generated at a specific alignment. The goal is to ensure that sequences of

...ed = false; } - static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value); namespace { +class DarwinAArch64AsmBackend : public AArch64AsmBackend { +public: + DarwinAArch64AsmBackend(const Target &T, const StringRef TT, uint8_t _OSABI) + : AArch64AsmBackend(T, TT) {} + bool mayNeedRelaxation(const MCInst &) const { return false; } + + virtual bool doesSectionRequireSymbols(const MCSection &Section) const { + SectionKind kind = Section.getKind(); + return kind.isDataRel() || kind.isReadOnlyWithRel() || kind.isMetadata() || + kind.isMergeableConst(); + } + + un...