search for: maxvl

...>>> >>>>> <scalable 1 x double> >>>>> >>>>> I know it won't map to an SVE type. I'm simply curious because >>>>> traditionally Cray machines defined vectors in terms of >>>>> machine-dependent "maxvl" with an element type, so with the above vscale >>>>> would == maxvl. Not that we make any such things anymore. But maybe >>>>> someone else does? >>>> >>>> That's legal in IR, yes, and we believe it should be usable to represent the...

...bit width? For example, is this legal? >>> >>> <scalable 1 x double> >>> >>> I know it won't map to an SVE type. I'm simply curious because >>> traditionally Cray machines defined vectors in terms of >>> machine-dependent "maxvl" with an element type, so with the above vscale >>> would == maxvl. Not that we make any such things anymore. But maybe >>> someone else does? >> >> That's legal in IR, yes, and we believe it should be usable to represent the vectors for >> RISC-V'...

...a scalable vector that requires a > minimum bit width? For example, is this legal? > > <scalable 1 x double> > > I know it won't map to an SVE type. I'm simply curious because > traditionally Cray machines defined vectors in terms of > machine-dependent "maxvl" with an element type, so with the above vscale > would == maxvl. Not that we make any such things anymore. But maybe > someone else does? That's legal in IR, yes, and we believe it should be usable to represent the vectors for RISC-V's 'V' extension. The main problem...

Hi David, Let me put the last two comments up: > > But we're trying to represent slightly different techniques > > (predication, vscale change) which need to be tied down to only > > exactly what they do. > > Wouldn't intrinsics to change vscale do exactly that? You're right. I've been using the same overloaded term and this is probably what caused the

...ething like this: > > loop top: > vl = getvl N # N contains the number of iterations left > <do computation> > N = N - vl > branch N > 0, loop top > > The "getvl" instruction would usually return the full hardware vector > register length (MAXVL), except on the 2nd-to-last iteration if N was > larger than MAXVL but less than 2*MAXVL it would return something like > <N % 2 == 0 ? N/2 : N/2 + 1>, so in the range (0, MAXVL). The last > iteration would then run at the same VL or one less depending on whether > N was odd or e...

Hi David, Thanks for taking a look. > On 5 Jun 2018, at 16:23, dag at cray.com wrote: > > Hi Graham, > > Just a few initial comments. > > Graham Hunter <Graham.Hunter at arm.com> writes: > >> ``<scalable x 4 x i32>`` and ``<scalable x 8 x i16>`` have the same number of >> bytes. > > "scalable" instead of "scalable

Hi David, Responses below. -Graham On 11 Jun 2018, at 22:19, David A. Greene <dag at cray.com<mailto:dag at cray.com>> wrote: Graham Hunter <Graham.Hunter at arm.com<mailto:Graham.Hunter at arm.com>> writes: ======== 1. Types ======== To represent a vector of unknown length a boolean `Scalable` property has been added to the `VectorType` class, which indicates that

Hi, i am the main author of RV, the Region Vectorizer (github.com/cdl-saarland/rv). I want to share our standpoint as potential users of the proposed vector-length agnostic IR (RISC-V, ARM SVE). -- support for `llvm.experimental.vector.reduce.*` intrinsics -- RV relies heavily on predicate reductions (`or` and `and` reduction) to tame divergent loops and provide a vector-length agnostic