search for: maxbus

...intf("unable to determine PCI bios cfg mechanism.\n"); + } + } + + return lastbus; +} + static char * skipspace(char *p) { @@ -205,13 +236,23 @@ static struct match * pciscan(struct match *list) { - unsigned int bus, dev, func, maxfunc; + unsigned int bus, dev, func, maxfunc, maxbus; uint32_t did, sid; uint8_t hdrtype, rid; pciaddr_t a; struct match *m; + int bios_maxbus; + + + if ((bios_maxbus = get_bios()) < 0) { + dprintf("PCI bios not detected.\n"); + maxbus = 0xff; + } else { + maxbus = bios_maxbus + 1; + dprintf("PCI bios repo...

...~(pgsz - 1); + pci_write_config_dword(dev, pos + PCI_IOV_SYS_PGSIZE, pgsz); + + iov = kzalloc(sizeof(*iov), GFP_KERNEL); + if (!iov) + return -ENOMEM; + + iov->cap = pos; + iov->total = total; + iov->offset = offset; + iov->stride = stride; + iov->align = pgsz << 12; + iov->maxbus = (dev->devfn + offset + stride * (total - 1)) >> 8; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; +...

...~(pgsz - 1); + pci_write_config_dword(dev, pos + PCI_IOV_SYS_PGSIZE, pgsz); + + iov = kzalloc(sizeof(*iov), GFP_KERNEL); + if (!iov) + return -ENOMEM; + + iov->cap = pos; + iov->total = total; + iov->offset = offset; + iov->stride = stride; + iov->align = pgsz << 12; + iov->maxbus = (dev->devfn + offset + stride * (total - 1)) >> 8; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; +...

...~(pgsz - 1); + pci_write_config_dword(dev, pos + PCI_IOV_SYS_PGSIZE, pgsz); + + iov = kzalloc(sizeof(*iov), GFP_KERNEL); + if (!iov) + return -ENOMEM; + + iov->cap = pos; + iov->total = total; + iov->offset = offset; + iov->stride = stride; + iov->align = pgsz << 12; + iov->maxbus = (dev->devfn + offset + stride * (total - 1)) >> 8; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; +...

...wd_enabled(pf)) + reg |= PCI_IOV_CTRL_ARI; + else + reg &= ~PCI_IOV_CTRL_ARI; + } else + reg &= ~(PCI_IOV_CTRL_VFE | PCI_IOV_CTRL_MSE); + + pci_write_config_word(pf, pf->iov->cap + PCI_IOV_CTRL, reg); + + ssleep(1); +} + +static int iov_init(struct pci_dev *pf) +{ + int i; + u16 maxbus; + u32 reg; + int err; + int pos = pf->iov->cap; + + iov_set_vfe(pf, 0); + + if (pf->iov->nr_virtfn == 0) + return 0; + + pci_write_config_word(pf, pos + PCI_IOV_NUM_VF, pf->iov->nr_virtfn); + + pci_read_config_dword(pf, pos + PCI_IOV_SUP_PGSIZE, &reg); + i = PAGE_SHIFT >...

...wd_enabled(pf)) + reg |= PCI_IOV_CTRL_ARI; + else + reg &= ~PCI_IOV_CTRL_ARI; + } else + reg &= ~(PCI_IOV_CTRL_VFE | PCI_IOV_CTRL_MSE); + + pci_write_config_word(pf, pf->iov->cap + PCI_IOV_CTRL, reg); + + ssleep(1); +} + +static int iov_init(struct pci_dev *pf) +{ + int i; + u16 maxbus; + u32 reg; + int err; + int pos = pf->iov->cap; + + iov_set_vfe(pf, 0); + + if (pf->iov->nr_virtfn == 0) + return 0; + + pci_write_config_word(pf, pos + PCI_IOV_NUM_VF, pf->iov->nr_virtfn); + + pci_read_config_dword(pf, pos + PCI_IOV_SUP_PGSIZE, &reg); + i = PAGE_SHIFT >...

...wd_enabled(pf)) + reg |= PCI_IOV_CTRL_ARI; + else + reg &= ~PCI_IOV_CTRL_ARI; + } else + reg &= ~(PCI_IOV_CTRL_VFE | PCI_IOV_CTRL_MSE); + + pci_write_config_word(pf, pf->iov->cap + PCI_IOV_CTRL, reg); + + ssleep(1); +} + +static int iov_init(struct pci_dev *pf) +{ + int i; + u16 maxbus; + u32 reg; + int err; + int pos = pf->iov->cap; + + iov_set_vfe(pf, 0); + + if (pf->iov->nr_virtfn == 0) + return 0; + + pci_write_config_word(pf, pos + PCI_IOV_NUM_VF, pf->iov->nr_virtfn); + + pci_read_config_dword(pf, pos + PCI_IOV_SUP_PGSIZE, &reg); + i = PAGE_SHIFT >...