Displaying 4 results from an estimated 4 matches for "max_pci_devic".
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max_pci_devices
2019 May 16
3
[PATCH 05/10] s390/cio: introduce DMA pools to cio
On Sun, 12 May 2019, Halil Pasic wrote:
> I've also got code that deals with AIRQ_IV_CACHELINE by turning the
> kmem_cache into a dma_pool.
>
> Cornelia, Sebastian which approach do you prefer:
> 1) get rid of cio_dma_pool and AIRQ_IV_CACHELINE, and waste a page per
> vector, or
> 2) go with the approach taken by the patch below?
We only have a couple of users for
2019 May 16
3
[PATCH 05/10] s390/cio: introduce DMA pools to cio
On Sun, 12 May 2019, Halil Pasic wrote:
> I've also got code that deals with AIRQ_IV_CACHELINE by turning the
> kmem_cache into a dma_pool.
>
> Cornelia, Sebastian which approach do you prefer:
> 1) get rid of cio_dma_pool and AIRQ_IV_CACHELINE, and waste a page per
> vector, or
> 2) go with the approach taken by the patch below?
We only have a couple of users for
2019 May 22
1
[PATCH 05/10] s390/cio: introduce DMA pools to cio
On Mon, 20 May 2019, Halil Pasic wrote:
> On Thu, 16 May 2019 15:59:22 +0200 (CEST)
> Sebastian Ott <sebott at linux.ibm.com> wrote:
> > We only have a couple of users for airq_iv:
> >
> > virtio_ccw.c: 2K bits
>
> You mean a single allocation is 2k bits (VIRTIO_IV_BITS = 256 * 8)? My
> understanding is that the upper bound is more like:
> MAX_AIRQ_AREAS
2019 May 20
0
[PATCH 05/10] s390/cio: introduce DMA pools to cio
On Thu, 16 May 2019 15:59:22 +0200 (CEST)
Sebastian Ott <sebott at linux.ibm.com> wrote:
> On Sun, 12 May 2019, Halil Pasic wrote:
> > I've also got code that deals with AIRQ_IV_CACHELINE by turning the
> > kmem_cache into a dma_pool.
> >
> > Cornelia, Sebastian which approach do you prefer:
> > 1) get rid of cio_dma_pool and AIRQ_IV_CACHELINE, and