search for: max_med

Add support for reclocking on GK20A, using a statically-defined pstates table. The algorithms for calculating the coefficients and setting the clocks are directly taken from the ChromeOS kernel. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 1 +

Hey Alex, Thanks. I have a couple of questions and remarks, but really, those should be treated as discussion points rather than anything else. Besides some inline comments, I was curious whether it is not necessary to pause PFIFO and the engines like done with at least NVA3-NVAF? Or is the transition smooth enough? op 10-07-14 09:34, Alexandre Courbot schreef: > Add support for

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

From: Tom Rix <trix at redhat.com> clang static analysis flags this problem hw.c:271:12: warning: The left operand of '>=' is a garbage value if (pv.M1 >= pll_lim.vco1.min_m ... ~~~~~ ^ This is mostly not a problem because an early check in nouveau_hw_fix_bad_vpll() if (nvbios_pll_parse(bios, pll, &pll_lim)) return; nouveau_hw_get_pllvals(dev, pll,

For some reason max_vco was set to a lower value that it can support, which prevented some clock states to be applied. Fix this by setting it to the same value as downstream. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- nvkm/subdev/clock/gk20a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c index

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

...end "info", "help", or "[un]subscribe" (in the "body", not the subject !) To: r-help-request at stat.math.ethz.ch _._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._ -------------- next part -------------- Ove_med Mag_med Cer_med Max_med 1 2.25 2.75 2.75 2.25 2 2 3.25 2.5 2.25 3 1.75 2.75 2.5 3 4 2 3.25 2.5 2.25 5 2.25 2.25 2.25 3.25 6 1 3.25 3.25 2.5 7 2.5 3 2.5 2 8 2 2.75 2.5 2.75 9 2.5 2.5 3 2 10 2.75 1.5 2.75 3 11 3.25 2.25 1.25 3.25 12 2 1.75 2.75 3.5 13 1 2.25 4 2.75 14 2 2.25 3.5 2.25 15 2.25 2 2.5 3.25 16 2...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it