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max_lat
2008 Dec 19
2
FW: [patch 0/4]Enable CMCI (Corrected Machine Check Error Interrupt) for Intel CPUs
...oth CMCI-support and NO-CMCI-support machine.
We test the patches combined with CPU online/offline ops and S3&S5 ops which cause banks owner changing
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Below notes might be helpful
1) CMCI use another apic_lvt entry (now max_lvt could be 6 in newer Intel platform)
2) CMCI is combined with polling mechanism since some CPUs don''t support CMCI. And for supporting CPUs, still some banks don''t support CMCI. So we keep polling mechanism.
3) MCA banks shares between cores/threads. For avoiding mis-ops, we need...