search for: max_freq

Displaying 14 results from an estimated 14 matches for "max_freq".

2014 Sep 04
1
[PATCH 4/8] fb/ramnve0: Disable FB before reclocking
...ouveau/core/subdev/fb/ramnve0.c > @@ -998,6 +998,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) > if (ret) > return ret; > > + ram_fb_disable(fuc); > + > ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; > ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; > > @@ -1061,6 +1063,9 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) > break; > } > > + if (!ret) > + ram_fb_enable(fuc); &...
2012 Dec 25
7
Using collectd: CPUFreq in dom0
Hello, I''ve tried to get the CPUFreq plugin of collectd running in dom0. But I mentioned that it isn''t so easy to get a file in sysfs on the rigth place. I know that the value has to come from hypervisor and I''ve seen the code in xenpm. The only value I need is "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq" which would create cpufreq.c. Can anyone
2014 Sep 04
0
[PATCH 4/8] fb/ramnve0: Disable FB before reclocking
...gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -998,6 +998,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) if (ret) return ret; + ram_fb_disable(fuc); + ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; @@ -1061,6 +1063,9 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) break; } + if (!ret) + ram_fb_enable(fuc); + return ret; } -- 1.9.3
2014 Jul 10
0
[PATCH 3/3] drm/gk20a: reclocking support
...v/timer.h> + +#include <nouveau_platform.h> + +static const u8 pl_to_div[] = { +/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ +/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, +}; + +/* All frequencies in Mhz */ +struct gk20a_clk_pllg_params { + u32 min_freq, max_freq; + u32 min_vco, max_vco; + u32 min_u, max_u; + u32 min_m, max_m; + u32 min_n, max_n; + u32 min_pl, max_pl; +}; + +static const struct gk20a_clk_pllg_params gk20a_pllg_params = { + .min_freq = 144, .max_freq = 2064, + .min_vco = 1000, .max_vco = 2064, + .min_u = 12, .max_u = 38, + .min_m = 1, .max_m...
2014 Jul 10
3
[PATCH 3/3] drm/gk20a: reclocking support
...m.h> > + > +static const u8 pl_to_div[] = { > +/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ > +/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, > +}; > + > +/* All frequencies in Mhz */ > +struct gk20a_clk_pllg_params { > + u32 min_freq, max_freq; > + u32 min_vco, max_vco; > + u32 min_u, max_u; > + u32 min_m, max_m; > + u32 min_n, max_n; > + u32 min_pl, max_pl; > +}; > + > +static const struct gk20a_clk_pllg_params gk20a_pllg_params = { > + .min_freq = 144, .max_freq = 2064, > + .min_vco = 1000, .max_vco = 2064...
2014 Jul 10
10
[PATCH 0/3] drm/gk20a: support for reclocking
This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down
2014 Sep 04
10
MEMX improvements + DDR 2/3 MR generation
Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone
2006 Oct 20
5
To symbian and speex developers! Building instructions
Hello to everyone! During building speex library for Symbian OS I encountered some problems. All thess problems can be solved by modifying the speex sources. I don't have access to SVN repository of speex, so I will just describe the changes to be done: 1) mmp file in symbian derictory misses windows.c sources. You need to add this string into speex.mmp: SOURCES windows.c 2) Symbian OS
2013 Nov 16
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...ruct nvaa_clock_priv *priv, u32 reg, + u32 clock, int *N, int *M, int *P) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll pll; + struct nouveau_clock *clk = &priv->base; + int ret; + + ret = nvbios_pll_parse(bios, reg, &pll); + if (ret) + return 0; + + pll.vco2.max_freq = 0; + pll.refclk = clk->read(clk, nv_clk_src_href); + if (!pll.refclk) + return 0; + + return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); +} + +static inline u32 +calc_P(u32 src, u32 target, int *div) +{ + u32 clk0 = src, clk1 = src; + for (*div = 0; *div <= 7; (*d...
2013 Nov 17
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...ruct nvaa_clock_priv *priv, u32 reg, + u32 clock, int *N, int *M, int *P) +{ + struct nouveau_bios *bios = nouveau_bios(priv); + struct nvbios_pll pll; + struct nouveau_clock *clk = &priv->base; + int ret; + + ret = nvbios_pll_parse(bios, reg, &pll); + if (ret) + return 0; + + pll.vco2.max_freq = 0; + pll.refclk = clk->read(clk, nv_clk_src_href); + if (!pll.refclk) + return 0; + + return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); +} + +static inline u32 +calc_P(u32 src, u32 target, int *div) +{ + u32 clk0 = src, clk1 = src; + for (*div = 0; *div <= 7; (*d...
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to
2018 Jan 16
0
[ANNOUNCE] intel-gpu-tools 1.21
...op opening the driver just to find the debugfs igt/perf_pmu: Test for supported perf before starting test_interrupts igt/perf_pmu: Tidy skip message for unsupported kernels igt/perf_pmu: Clear errno in between invalid atrr tests igt/perf_pmu: Explicitly reset min_freq before max_freq igt/perf_pmu: Protect macro args igt/perf_pmu: Avoid underflow in measured_sleep() igt/perf_pmu: Bump batch_duration for legacy sampling inaccuracy igt/perf_pmu: Reduce arbitrary delays before rc6 igt/perf_pmu: Stop peeking at intel_mmio registers igt/perf_pmu: R...
2012 Jul 22
20
Kernel crash with acpi_processor, cpu_idle and intel_idle =y
Hi everyone, When I set CONFIG_ACPI_PROCESSOR, CONFIG_CPU_IDLE and CONFIG_INTEL_IDLE to y then I cannot boot Xen; there is a crash. If I turn CONFIG_INTEL_IDLE off then the boot goes well and, after dom0 has booted, xenpm works and gives some sane output, see below. I have tested this with kernels 3.2 to 3.4.6. Is it impossible to use INTEL_IDLE with Xen? If this is a known issue then maybe
2012 Jul 22
20
Kernel crash with acpi_processor, cpu_idle and intel_idle =y
Hi everyone, When I set CONFIG_ACPI_PROCESSOR, CONFIG_CPU_IDLE and CONFIG_INTEL_IDLE to y then I cannot boot Xen; there is a crash. If I turn CONFIG_INTEL_IDLE off then the boot goes well and, after dom0 has booted, xenpm works and gives some sane output, see below. I have tested this with kernels 3.2 to 3.4.6. Is it impossible to use INTEL_IDLE with Xen? If this is a known issue then maybe