search for: matchregisternam

...riable-sized register classes is the case where you have multiple registers with the same AsmName. This crops up in the same kind of cases where you have multiple instructions with the same encoding. Without a workaround, an assert is tripped in llvm-tblgen when trying to produce a StringSwitch for MatchRegisterName. The solution in Mips, PPC and others seems to be involve the generation of MatchRegisterName. What has been discussed so far with regards to HwMode and variable-size register classes points to a solution, but I don't think it's quite enough. Options include: 1. Only have one set of regis...

...rser.o)(.text+0x5d8): In function `(anonymous namespace)::ARMAsmParser::ParseDirective(llvm::AsmToken)': : undefined reference to `__assert' /tmp/llvm-build/2.7/llvm-objects/Release/lib/libLLVMARMAsmParser.a(ARMAsmParser.o)(.text+0xd10): In function `(anonymous namespace)::ARMAsmParser::MatchRegisterName(llvm::StringRef const&)': : undefined reference to `memcmp' /tmp/llvm-build/2.7/llvm-objects/Release/lib/libLLVMARMAsmParser.a(ARMAsmParser.o)(.text+0xd45): In function `(anonymous namespace)::ARMAsmParser::MatchRegisterName(llvm::StringRef const&)': : undefined reference to...

On Thu, Apr 29, 2010 at 6:31 PM, Jeffrey Yasskin <jyasskin at google.com> wrote: > On Wed, Apr 28, 2010 at 10:48 AM, Yuri <yuri at tsoft.com> wrote: >> Jeffrey Yasskin wrote: >>> >>> We currently use two different techniques to get whole libraries >>> included into the .so. On Linux (gnu ld and gold), we pass >>> --whole-archive, while on

...ails: >cat test_bad.s mov eax, flags >llvm-mc.exe -x86-asm-syntax=intel test_bad.s -o - test_bad.s:1:1: error: invalid operand for instruction mov eax, flags ^ .text After investigation, I saw that the memory location named "flags" was matched to the EFLAGS register in the MatchRegisterName() function in the generated X86GenAsmMatcher.inc. case 'f': // 1 string to match. if (memcmp(Name.data()+1, "lags", 4)) break; return 25; // "flags" So basically, what I'm seeing with "flags" (which should be a legit variable nam...

...In function `(anonymous > namespace)::ARMAsmParser::ParseDirective(llvm::AsmToken)': > : undefined reference to `__assert' > /tmp/llvm-build/2.7/llvm-objects/Release/lib/libLLVMARMAsmParser.a(ARMAsmParser.o)(.text+0xd10): > In function `(anonymous > namespace)::ARMAsmParser::MatchRegisterName(llvm::StringRef const&)': > : undefined reference to `memcmp' > /tmp/llvm-build/2.7/llvm-objects/Release/lib/libLLVMARMAsmParser.a(ARMAsmParser.o)(.text+0xd45): > In function `(anonymous > namespace)::ARMAsmParser::MatchRegisterName(llvm::StringRef const&)': > :...

...xe -x86-asm-syntax=intel test_bad.s -o - > > test_bad.s:1:1: error: invalid operand for instruction > > mov eax, flags > > ^ > > .text > > > > After investigation, I saw that the memory location named “flags” was > matched to the EFLAGS register in the MatchRegisterName() function in the > generated X86GenAsmMatcher.inc. > > > > case 'f': // 1 string to match. > > if (memcmp(Name.data()+1, "lags", 4)) > > break; > > return 25; // "flags" > > > > So basically, what I’...

...llvm-mc fails: >cat test_bad.s mov eax, flags >llvm-mc.exe -x86-asm-syntax=intel test_bad.s -o - test_bad.s:1:1: error: invalid operand for instruction mov eax, flags ^ .text After investigation, I saw that the memory location named “flags” was matched to the EFLAGS register in the MatchRegisterName() function in the generated X86GenAsmMatcher.inc. case 'f': // 1 string to match. if (memcmp(Name.data()+1, "lags", 4)) break; return 25; // "flags" So basically, what I’m seeing with “flags” (which should be a legit variable name) is that the...

...disambiguate which instruction should be selected. It sounds like MIPS 64vs.32 does things the other way around and uses the mnemonic to disambiguate what the operands mean. You may be able to work around this a bit w/ some tblgen hacking. First, you'll need to disable the TableGen emission of MatchRegisterName(), which is almost certainly where this is running into trouble. That's currently unconditionally generated, and will need parameterized. Second, you'll need to have your register name matcher explicitly check for all the valid reg names complete w/ context to disambiguate. The ARM backend...

...xe -x86-asm-syntax=intel test_bad.s -o - > > test_bad.s:1:1: error: invalid operand for instruction > > mov eax, flags > > ^ > > .text > > > > After investigation, I saw that the memory location named “flags” was > matched to the EFLAGS register in the MatchRegisterName() function in the > generated X86GenAsmMatcher.inc. > > > > case 'f': // 1 string to match. > > if (memcmp(Name.data()+1, "lags", 4)) > > break; > > return 25; // "flags" > > > > So basically, what I’...

...-x86-asm-syntax=intel test_bad.s -o - > > test_bad.s:1:1: error: invalid operand for instruction > > mov eax, flags > > ^ > > .text > > > > After investigation, I saw that the memory location named “flags” was matched to the EFLAGS register in the MatchRegisterName() function in the generated X86GenAsmMatcher.inc. > > > > case 'f': // 1 string to match. > > if (memcmp(Name.data()+1, "lags", 4)) > > break; > > return 25; // "flags" > > > > So basically, w...

I believe that table gen builds MipsGenAsmMatcher.inc which has the Match routines like MatchRegisterName(). In building MipsGenAsmMatcher.inc I am hitting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence: /home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero' d...

...my backend. llvm-tablegen also generates asm-matcher .inc file without any error. I have included the .inc file in my class for AsmParser. However, while building llvm, in linking stage for LTO, i am getting error - undefined reference to functions - ComputeAvailableFeatures, MatchInstructionImpl, MatchRegisterName and convertToMapAndConstraints. I see these functions declared and defined in GenAsmMatcher.inc file which i have included in my AsmParser class. Still i am getting the error. I may be missing something very basic. Can someone please help in resolving this error? Thanks. Regards, Alex -------...

I'm trying to build a standalone assembler for Mips using AsmParser. Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. I am getting an assertion for what I believe are multiple register definitions with the same name. llvm-tblgen:

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set

.../// { - bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands, - MCInst &Inst); + virtual bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands, + MCInst &Inst); /// MatchRegisterName - Match the given string to a register name and return /// its register number, or -1 if there is no match. To allow return values @@ -94,13 +85,14 @@ private: public: - ARMAsmParser(const Target &T, MCAsmParser &_Parser) - : TargetAsmParser(T), Parser(_Parser) {} + ARMAsmPar...