search for: matchoperandparserimpl

...instruction on processors that don't support it, the asm parser says: /tmp/foo.s:1:2: error: invalid operands for instruction sllk %r2,%r3,1 ^ rather than: /tmp/foo.s:1:2: error: instruction requires: distinct-ops sllk %r2,%r3,1 ^ This is because MatchOperandParserImpl() skips custom parsers if the subtarget feature isn't enabled, so the instruction is parsed using the default operand parser instead. Then MatchInstructionImpl() only returns Match_MissingFeature if an otherwise good match is found, which in my case requires the custom parser to be used. ARM...

...eAsm, unsigned VariantID = 0); enum OperandMatchResultTy { MatchOperand_Success, // operand matched successfully MatchOperand_NoMatch, // operand did not match MatchOperand_ParseFail // operand matched but had errors }; OperandMatchResultTy MatchOperandParserImpl( SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic); OperandMatchResultTy tryCustomParseOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned MCK); #endif // GET_ASSEMBLER_HEADER_INFO -------------- next part -------------- An HTM...

...unsigned VariantID = 0); > > enum OperandMatchResultTy { > MatchOperand_Success, // operand matched successfully > MatchOperand_NoMatch, // operand did not match > MatchOperand_ParseFail // operand matched but had errors > }; > OperandMatchResultTy MatchOperandParserImpl( > SmallVectorImpl<MCParsedAsmOperand*> &Operands, > StringRef Mnemonic); > OperandMatchResultTy tryCustomParseOperand( > SmallVectorImpl<MCParsedAsmOperand*> &Operands, > unsigned MCK); > > #endif // GET_ASSEMBLER_HEADER_INFO My understan...

> /tmp/foo.s:1:2: error: instruction requires: distinct-ops > sllk %r2,%r3,1 > ^ That seems like it would be a good improvement for all targets. > ARM seems to rely on the current MatchOperandParserImpl() behaviour, > so I'm not going to suggest changing it unconditionally. Presumably you switched it and looked at what fell over; do you remember what kind of problems ARM had? Perhaps we can fix ARM so that your change works there too. Don't worry if not, I can try poking it myself bas...

...t; /tmp/foo.s:1:2: error: instruction requires: distinct-ops >> sllk %r2,%r3,1 >> ^ > > That seems like it would be a good improvement for all targets. Thanks, sounds like it might be more acceptable than I thought :-) >> ARM seems to rely on the current MatchOperandParserImpl() behaviour, >> so I'm not going to suggest changing it unconditionally. > > Presumably you switched it and looked at what fell over; do you > remember what kind of problems ARM had? Perhaps we can fix ARM so that > your change works there too. Yeah, there were two new MC fai...

...ecause 0.5 is this case contiune; before the statement to empty the modifier (RegOp.setModifiers(0);), it obvious does not work and cause the other matching fails. Does it mean to modify other files in other places, such as the VOP3Inst in the SIInstrInfo.td, or is this nothing to do with the MatchOperandParserImpl method or the other tablegen'd files. I'll be grateful for any idea you might give me to work around this. Regards, 李弘宇 (Li, Hong-Yu) Department of Computer Science & Information Engineering National Taiwan University -Matt -------------- next part -------------- An HTML attachment...

...acceptable than I thought :-) FWIW, I'm the guy to blame for the current implementation and I like the idea. Getting it right may be marginally tricky, but the direction is good. Better diagnostics from the assemblers is a very good thing. > >>> ARM seems to rely on the current MatchOperandParserImpl() behaviour, >>> so I'm not going to suggest changing it unconditionally. >> >> Presumably you switched it and looked at what fell over; do you >> remember what kind of problems ARM had? Perhaps we can fix ARM so that >> your change works there too. > >...

Dear Developers, I compile a OpenCL kernel, FFT, in AMDAPP SDK v2.5 using clang 3.8 + libclc and assembling the code with lld (The LLVM linker). The assembly code contains the following assembly codes (and lots of other similar format assembly) that fails to be parsed by AMDGPUAsmParser. It seems to me that both are valid instructions after looking at the SI instruction spec. s_mov_b32 s0,