search for: matchabl

Hi, In AsmMatcherEmitter.cpp, the operator “<” for comparing matchables (MatchableInfo objects) only checks matches that require more features as the last rule. I would like to propose that we check for that rule earlier, in the case of unrelated UserClasses, before we decide to set precedence based on UserClass name. The motivation is that unrelated UserClasses...

Hello, InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: if (!Hack) PrintFatalError(TheDef->getLoc(), "ERROR: matchable with tied operand '" + Tok + "' can never be matched!"); // FIXME: Should reject these. The ARM backend hits this with $lane in a // bunch of instructions. It is unclear what the right answer is. … Is there a way to fix this limi...

...; > InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. > > It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: > > if (!Hack) > PrintFatalError(TheDef->getLoc(), > "ERROR: matchable with tied operand '" + Tok + > "' can never be matched!"); > // FIXME: Should reject these. The ARM backend hits this with $lane in a > // bunch of instructions. It is unclear what the right answer is. > … > > Is there a...

...mitter.cpp @@ -1526,7 +1526,7 @@ void AsmMatcherInfo::buildInfo() { II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst); // Validate the alias definitions. - II->validate(CommentDelimiter, false); + II->validate(CommentDelimiter, true); Matchables.push_back(std::move(II)); } On 2017-12-15 03:40, Daniel Sanders wrote: > Hi, > > On Instructions you can use checkEarlyTargetMatchPredicate() to check > that the operands are the same. There's an example of that in > MipsAsmParser.cpp for DATI and DAHI. I can't th...

...onnected: user=<luna>, method=PLAIN, rip=217.147.235.52, lip=81.16.98.99 dovecot: Nov 30 09:09:51 Info: pop3-login: Disconnected: user=<luke>, method=PLAIN, rip=217.147.235.52, lip=81.16.98.99 -------CUT------- Googling the web I found that PAM based authentication obviously gives a matchable error message, but for some reasons the ldap backend does not - or does it? Any pointers highly appreciated :-) dovecot -n says this: -------CUT------- # 1.0.15: /etc/dovecot/dovecot.conf log_path: /var/log/dovecot.log protocols: imaps imap pop3 listen: 81.16.98.99 ssl_listen(default): 81.16.9...

...support for complex multiply is doable with either mechanism. Your statement made it sound like intrinsics were needed to *avoid* simplifcations in order to match them to hardware instructions and that a first-class complex type (using "normal" LLVM arithmetic instructions) would not be matchable to some hardware instructions. I was curious about what those cases would be. -David

...bstractly, by operator). That's pretty fundamental to how it works, so sticking with that would be good unless you want to write an entirely new algorithm. You could probably stick with the current basic stuff with some fiddling in tablegen where the asm string gets split apart when building up matchables to re-order things appropriately. Then your ParseInstruction() implementation would do similar tricks. The printer should "just work," thankfully. That said, you'll also likely have to do a bit of work in the generic AsmParser code, as it'll likely look at statements like these...

Hi, I'm trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward. But.. Hexagon assembly does not follow the "Mnemonic Rx Rx ." format that is expected by the assembly parsing infrastructure, represented by: StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); This

...o "select-safe-inputs-on-masked-off-lanes + fp-operation" pattern. If you emit that pattern to early, InstCombine etc might fold it away.. also because IR optimizations can not distinguish between a select that was part of the original program and a select that was inserted to have a matchable pattern in the backend. >>> My context for these questions is that my experience recently w/o >>> existing masked intrinsics shows us missing fairly basic >>> optimizations, precisely because they weren't able to reuse all of the >>> existing infrastructure...

...support for complex multiply is doable with either mechanism. Your statement made it sound like intrinsics were needed to *avoid* simplifcations in order to match them to hardware instructions and that a first-class complex type (using "normal" LLVM arithmetic instructions) would not be matchable to some hardware instructions. I was curious about what those cases would be. -David

...lowing problem: I''d like to do some multiple Comparisons between different factor levels (two factors, each with some 5 or 6 levels), because there are some significant interactions between these two factors. In S-plus 5, there is the function "multicomp", but in R, there ist no matchable funktion, as far as I could find out. So I ask you: What would you do in similar situations? Thanks very much for your answer. Regards -- Ruth Meili <meili at stat.math.ethz.ch> Seminar fuer Statistik, LEO D6 ETH (Federal Inst. Technology) 8092 Zurich SWITZERLAND phone: x-41-1-632-3505...

Hi, We are processing lots of calls and I want to filter these that have incomplete numbers sent with a proper SIP response. These numbers are not in the local dialplan by themselves, so I'm trying to find a way to generate 484 "Address Incomplete" SIP response based on the length of the extension called. Congestion response is too lossy of the original cause and doesn't

Has anyone got a method for limiting the total number of bytes transfered with rsync? I was thinking running with -n and then using the output to check how much will been transfered. I ask because a client had a broken filesystem that occasionally has 2T+ files on it (broken filesystem, so they weren't actually that big) but we happily ran up a huge b/w bill with rsync. -Mike

...one that fills with undef and one that fills with zero. Using a general vector operand with a restriction on valid values seems odd and potentially misleading. Another option is to always fill with undef and require a select on top of the load to fill with zero. The load + select would be easily matchable to a target instruction. I'm trying to think beyond just AVX-512 to what other future architectures might want. It's not a given that future architectures will fill with zero *or* undef though those are the two most likely fill values. -David ---------------...

Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes: > Some architectures have instructions that assist with complex > arithmetic. Without intrinsics it may be hard to use such > instructions especially because of the arithmetic simplifications. > Perhaps, depending on TTI, those intrinsics could be expanded into the > explicit arithmetic? Can you provide

Hello, I don't know much about Samba so forgive me if this is a stupid question. I'm currently working on a project for a client that relies on Unix machines for their main applications. Access to Unix applications is done through terminal emulation (vt 100) on Windows PCs. We are implementing a Windows NT network for file an print sharing and to support SMS. One of the goals of the

I am implementing a new backend and am pretty sure I don't quite understand "the way" one is supposed to implement conditional branches. My target CPU natively supports a conditional branch instruction that accepts a condition to test (equal, less than, etc.), two operands (two registers, or one register and one immediate), and finally a target PC to branch to if the comparison

...one that fills with undef and one that fills with zero. Using a general vector operand with a restriction on valid values seems odd and potentially misleading. Another option is to always fill with undef and require a select on top of the load to fill with zero. The load + select would be easily matchable to a target instruction. I'm trying to think beyond just AVX-512 to what other future architectures might want. It's not a given that future architectures will fill with zero *or* undef though those are the two most likely fill values. -David _______________...

...am unaffiliated and uninvolved with this proposal), it appears clearly beneficial for LLVM to have a libc if it were done well. That said, clang shouldn’t/couldn't *require* one specific libc, just like we don’t require libc++ as the standard library. We want LLVM components to be mixable and matchable. I appreciate the comments on this thread that are throwing in ideas for how to make the project better, how to ensure it grows to being a successful and widely useful component of LLVM, etc. I for one think that this could be very useful for people building custom micro targets, and being able...

...nt code in X86ISelLowering. I don't really see where you're going with this. I agree that there is confusing and fragile code for shuffle lowering, but this is what Bruno is working on fixing. To me, the problem is that legalize of SHUFFLE_VECTOR eliminates shuffles that are not directly matchable into a single machine instruction, but preserves ones that do match. This means that there is duplicated code in both legalize and isel that has to know that a shuffle is an "unpacklps" or whatever. Other parts of the code that generate shuffles generally know exactly what shuffle they...