Displaying 5 results from an estimated 5 matches for "maskedvalueiszero".
2010 Jan 05
0
[LLVMdev] [llvm-commits] [llvm] r92458 - in /llvm/trunk: lib/Target/README.txt lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/or.ll
...mp; C1) | (V & C2) --> (V|N) & (C1|C2)
>> + // iff (C1&C2) == 0 and (N&~C1) == 0
>> + if ((C1->getValue() & C2->getValue()) == 0) {
>> + if (match(A, m_Or(m_Value(V1), m_Value(V2))) &&
>> + ((V1 == B && MaskedValueIsZero(V2, ~C1->getValue())) || // (V|N)
>> + (V2 == B && MaskedValueIsZero(V1, ~C1->getValue())))) // (N|V)
>> + return BinaryOperator::CreateAnd(A,
>> + ConstantInt::get(A->getContext(),
>> +...
2015 Nov 02
2
Questions about load/store incrementing address modes
Thanks again for your help Steve,
I’m thinking perhaps my “SelectADDRrr” pattern is inadequate. The sign-extension is at the hardware level, the code generator sees (should see) it as a 16-bit signed register value. My implementation is just:
bool SHAVEISelDAGtoDAG::SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset) {
if ((Addr.getOpcode() == ISD::ADD) {
Base
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...ote the condition.
+ Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
- // The top bits of the promoted condition are not necessarily zero, ensure
- // that the value is properly zero extended.
- unsigned BitWidth = Tmp2.getValueSizeInBits();
- if (!DAG.MaskedValueIsZero(Tmp2,
- APInt::getHighBitsSet(BitWidth, BitWidth-1)))
- Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
- break;
- }
- }
-
// Basic block destination (Op#2) is always legal.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->ge...