search for: mask_vr

...andled similar (for the sake of making the example shorted I replaced your sequence of IR instruction by one “virtual” IR instruction): x = predicated_add %mask, %x, %y, %oldvalue This (actually, your sequence of selects, and add) would be matched during ISel to: vr0<def, tied1> = PRED_ADD mask_vr, vr1<use>, vr2<use>, vr3<use, tied0> >From here on the machinery is the same, the two-address pass would translate such instructions to: vr0 = vr3 vr0 = PRED_ADD mask_vr, vr1, vr2, vr0 If vr3 is not live after PRED_ADD coalescing will coalesce vr0 and vr3. I don’t think ther...

...e of making the example shorted I replaced your sequence of IR instruction by one “virtual” IR instruction): > > x = predicated_add %mask, %x, %y, %oldvalue > > This (actually, your sequence of selects, and add) would be matched during ISel to: > > vr0<def, tied1> = PRED_ADD mask_vr, vr1<use>, vr2<use>, vr3<use, tied0> > > From here on the machinery is the same, the two-address pass would translate such instructions to: > > vr0 = vr3 > vr0 = PRED_ADD mask_vr, vr1, vr2, vr0 > > If vr3 is not live after PRED_ADD coalescing will coalesce vr0...

On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether

I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the