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ivtm <martinaide1 at yahoo.com> writes: > Another question, I need to get the "%0" below in the: > > %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] > > that is, the return register. What information do you want, exactly? In your example, %0 is the CallInst. S...

...t always need to extract all the components of an > instruction. (I've looked at the interpreter too, but it is doing other > stuff). > > Anyway..concretely, I need to extract the return register for an > instruction. > > > > Óscar Fuentes wrote: >> ivtm <martinaide1 at yahoo.com> writes: >> >>> Another question, I need to get the "%0" below in the: >>> >>> %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] >>> >>> that is, the return register. >> What information do yo...

...ll relevant info that they need, they do not always need to extract all the components of an instruction. (I've looked at the interpreter too, but it is doing other stuff). Anyway..concretely, I need to extract the return register for an instruction. Óscar Fuentes wrote: > > ivtm <martinaide1 at yahoo.com> writes: > >> Another question, I need to get the "%0" below in the: >> >> %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] >> >> that is, the return register. > > What information do you want, exactly? >...

ivtm <martinaide1 at yahoo.com> writes: > I am wondering if there are options that can be given to LLVM can be used to > generate code that is not in SSA, but in plain 3-address form ? (for > example, if there is an existing pass that does the register allocation and > dead variable elimination) &gt...

Hi, I am wondering if there are options that can be given to LLVM can be used to generate code that is not in SSA, but in plain 3-address form ? (for example, if there is an existing pass that does the register allocation and dead variable elimination) For example, if I have: int x = 0; void main() { x++; x++; } I guess, if that is not the case, then, one needs to write their own pass.

...ly as a front end to translate to .bc files and then I have my own parser from there. At any rate, is there an option to the llvm-gcc --emit-llvm to tell it to produce .bc files that are at least space optimized (or even better, not in SSA form) ? thanks Óscar Fuentes wrote: > > ivtm <martinaide1 at yahoo.com> writes: > >> I am wondering if there are options that can be given to LLVM can be used >> to >> generate code that is not in SSA, but in plain 3-address form ? (for >> example, if there is an existing pass that does the register allocation >> and...

...always in SSA form. If you *really* don't want it to be, use allocas for everything and then don't run the mem2reg optimization pass. This will represent all of your variables as stack locations instead of registers, and it will not be SSA. Reid On Sat, Sep 26, 2009 at 3:55 PM, ivtm <martinaide1 at yahoo.com> wrote: > > I tried the -O0 option and I am still getting output in SSA form: > > I do: > llvm-gcc -O0 -emit-llvm -c x.c -o x.bc, > > and then: > > llvm-dis x.bc > > > > > Anton Korobeynikov-2 wrote: >> >>> At any rate, is the...

...nts of an >> instruction. (I've looked at the interpreter too, but it is doing other >> stuff). >> >> Anyway..concretely, I need to extract the return register for an >> instruction. >> >> >> >> Óscar Fuentes wrote: >>> ivtm <martinaide1 at yahoo.com> writes: >>> >>>> Another question, I need to get the "%0" below in the: >>>> >>>> %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] >>>> >>>> that is, the return register. >&gt...

...nts of an >> instruction. (I've looked at the interpreter too, but it is doing other >> stuff). >> >> Anyway..concretely, I need to extract the return register for an >> instruction. >> >> >> >> Óscar Fuentes wrote: >>> ivtm <martinaide1 at yahoo.com> writes: >>> >>>> Another question, I need to get the "%0" below in the: >>>> >>>> %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] >>>> >>>> that is, the return register. >&gt...

I tried the -O0 option and I am still getting output in SSA form: I do: llvm-gcc -O0 -emit-llvm -c x.c -o x.bc, and then: llvm-dis x.bc Anton Korobeynikov-2 wrote: > >> At any rate, is there an option to the llvm-gcc --emit-llvm to tell it to >> produce .bc files that are at least space optimized (or even better, not >> in >> SSA form) ? > Yes, -O0 > >

...* don't want it to be, > use allocas for everything and then don't run the mem2reg optimization > pass. This will represent all of your variables as stack locations > instead of registers, and it will not be SSA. > > Reid > > On Sat, Sep 26, 2009 at 3:55 PM, ivtm <martinaide1 at yahoo.com> wrote: >> >> I tried the -O0 option and I am still getting output in SSA form: >> >> I do: >> llvm-gcc -O0 -emit-llvm -c x.c -o x.bc, >> >> and then: >> >> llvm-dis x.bc >> >> >> >> >> Anton Korobey...

Another question, I need to get the "%0" below in the: %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] that is, the return register. I am wondering in general, where should I look in the llvm codebase for parsing instructions ? I am looking at existing passes and also the header files like Function.h, etc to see what methods they have, but it takes a while

Hi Nick, Thanks, that seemed to work. Nick Lewycky wrote: > > ivtm wrote: >> I am processing the LLVM instructions and right now I am at the 'call' >> instruction. >> For now I just want to print the argument type. >> >> For example in the following: >> >> %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1]

I am processing the LLVM instructions and right now I am at the 'call' instruction. For now I just want to print the argument type. For example in the following: %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] I need to get access to 'i32' and '8' separately. I do: CallInst *CI = dyn_cast<CallInst>(I); Value *v = CI->getOperand(1)