search for: marm

Displaying 20 results from an estimated 41 matches for "marm".

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2011 Aug 10
0
exiting with ogg.h missing
...----------------------------------------------------------------------------------------------------------------------------------- /opt/linaro-gcc-4.5-arm-linux-gnueabi-32bit/bin/arm-linux-gnueabi-gcc -DHAVE_CONFIG_H -I. -I.. -I../include -I.. -I/root/dump/include -I../libogg-1.3.0/include/ -marm -fvisibility=hidden -MT testjitter.o -MD -MP -MF .deps/testjitter.Tpo -c -o testjitter.o testjitter.c mv -f .deps/testjitter.Tpo .deps/testjitter.Po /bin/bash ../libtool --tag=CC --mode=link /opt/linaro-gcc-4.5-arm-linux-gnueabi-32bit/bin/arm-linux-gnueabi-gcc -I../libogg-1.3.0/include/ -marm...
2018 Nov 15
2
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
...her a gcc toolchain defaults to ARM or Thumb is a configuration time decision by whomever builds the toolchain. The linaro arm-linux-gnueabihf toolchain I have defaults to -mthumb and that doesn't vary for -mcpu or any other command line option. I haven't got a gcc to hand that defaults to -marm so that I can test whether -mcpu=cortex-m3 will change that to Thumb. If I try -marm -mcpu=cortex-m3 I get "error: target CPU does not support ARM mode". Can you give us a more concrete example about where GCC is inconsistent? For clang I'm not particularly fond of -Oz implying a ch...
2018 Nov 15
2
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
...her a gcc toolchain defaults to ARM or Thumb is a configuration time decision by whomever builds the toolchain. The linaro arm-linux-gnueabihf toolchain I have defaults to -mthumb and that doesn't vary for -mcpu or any other command line option. I haven't got a gcc to hand that defaults to -marm so that I can test whether -mcpu=cortex-m3 will change that to Thumb. If I try -marm -mcpu=cortex-m3 I get "error: target CPU does not support ARM mode". Can you give us a more concrete example about where GCC is inconsistent? For clang I'm not particularly fond of -Oz implying a ch...
2018 Nov 15
3
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
...ill also give you thumb code if you compile with -O3 though. It is a toolchain default and not an implication of -Os or -Oz. My vote is not imply ARM/Thumb state changes with optimization options. We've already got two ways to do it --target=thumb-none-eabi, --target=arm-none-eabi and -mthumb/-marm I think the potential confusion outweighs the potential benefit. I'm just one voice though. Peter ________________________________ > From: Sjoerd Meijer > Sent: 15 November 2018 14:15:26 > To: Peter Smith; Bruce Hoult > Cc: llvm-dev; nd > Subject: Re: [cfe-dev] [RFC][ARM] -Oz i...
2011 Aug 09
4
not building with --enable-arm-asm -enable-arm5e-asm
Hi, I am getting the following dump while trying to build for arm ./configure --prefix=/root/dump --host=arm-linux --with-gnu-ld --disable-static --enable-fixed-point --enable-arm-asm -enable-arm5e-asm configure: WARNING: unrecognized options: --enable-arm-asm Type "make; make install" to compile and install Speex root at rony-ubuntu:~/speex# make make all-recursive make[1]:
2018 Nov 15
3
[cfe-dev] [RFC][ARM] -Oz implies -mthumb
I've never tried -mcpu=cortex-xyz but I know -march=armv7 defaults to Thumb OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: arm-linux-gnueabihf-gcc (Ubuntu/Linaro 7.3.0-27ubuntu1~18.04) 7.3.0 cortex-m0 fails because it doesn't do hard float. I don't have an eabi compiler around. On Thu, Nov 15, 2018 at 4:14 AM, Tim
2011 Jun 26
2
[LLVMdev] Recommended GCC version for ARM/Linux platform for LLVM compilation.
...1]. With this and with just -O1 as optimize option I've been able to get to 1 failing testcase. Other tested were 4.4.3 and 4.5.2 and with default -O3 I'm on about 100 (4.5.2 being the worst compiler here) of failing testcases (those compilers generates thumb by default) and with "-marm -O1" as optimize option I'm on 28 (4.5.2) and 18 (4.4.3) failing testcases. (-marm being better than -mthumb) (also here[2]) So I'm curious what's *the* recommended compiler on this platform which LLVM development is using? Thanks! Karel [1]: http://ghcarm.wordpress.com/2011/0...
2013 Apr 12
1
[LLVMdev] arm machine code with clang 3.2
...s to generate ARM for Raspberry pi for LLVM 3.2 with clang 3.2? I realized that "-ccc-host-triple" is no longer valid option in clang. p.s. I googled and found the following which doesn't work with clang 3.2. To cross-compile for Raspberry Pi add flags -ccc-host-triple arm-eabi -marm -mfpu=vfp -mcpu=arm1176jzf-s -mtune=arm1176jzf-s -mfloat-abi=softfp -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130412/1b3d23ca/attachment.html>
2012 Oct 15
3
Problema con función readSIAR del paquete solaR
...eExtra Loading required package: RColorBrewer Loading required package: zoo Attaching package: ?zoo? The following object(s) are masked from ?package:base?: as.Date, as.Date.numeric Time Zone set to UTC. > readSIAR(4,1,'1/1/1970','31/12/2011') Downloading data from www.marm.es/siar... Error en read.table(file, ...) : more columns than column names > readSIAR(28,3,'01/01/2008','31/12/2008') Downloading data from www.marm.es/siar... Error en read.table(file, ...) : more columns than column names -------- Fin del corte desde la consola ---------- No...
2015 Sep 16
2
Arm: disabling/disallowing Thumb instructions
...piling a C file, not an object file produced by GHC compiling a Haskell file. GHC on Linux uses GCC by default to compile C (GHC's runtime system is written in C) and LLC/OPT when compiling Haskell code. For some reason gcc on armhf/linux by default produces Thumb code. GCC needs to be passed -marm on the command line to force production of pure Arm code. This has finally got me to the bottom on one of the most difficult bugs I've ever worked on. Cheers, Erik -- ---------------------------------------------------------------------- Erik de Castro Lopo http://www.mega-nerd.com/
2011 Mar 14
0
[LLVMdev] LLVM 2.9 RC1 Pre-release Tarballs
...here are LLVM 2.9 RC1 pre-release tarballs source available. You can find them here: > llvm 2.9rc1 test on Dualcore ARM running Ubuntu Natty gunzip llvm-2.9rc1.src.tar.gz tar zxvf llvm-2.9rc1.src.tar cd llvm-2.9-build ../llvm-2.9rc1/configure --enable-shared time make clean ;time make CXXFLAGS=-marm CFLAGS=-marm xranby at panda:/media/dh0/llvm-2.9-build$ time make check Failing Tests (64): LLVM :: CodeGen/CellSPU/2009-01-01-BrCond.ll LLVM :: CodeGen/CellSPU/call_indirect.ll LLVM :: CodeGen/CellSPU/extract_elt.ll LLVM :: CodeGen/CellSPU/fcmp64.ll LLVM :: CodeGen/CellSPU/fn...
2014 Apr 22
2
[LLVMdev] SCEV and induction variable identification
Hi Fellows, The goal is to find the induction variable for a loop, where the induction variable increments with the multiplication, division or shift operations, like this one: sz = 8; do { ... ... sz = sz / 2; } while (sz) Is SCEV capable of detecting the induction variable 'sz' in this case? The code snippet I am using to solve the problem is for each basic-block in a
2012 Sep 05
3
[LLVMdev] Unaligned vector memory access for ARM/NEON.
...I compile this program with clang -O3 -ccc-host-triple armv7-none-linux-gnueabi -mfpu=neon -mllvm -vectorize, the intermediate LLVM assembly looks OK (and it has an align 2 vector load), but the generated ARM assembly has the scalar loads. When I compile with (4.6) gcc -std=c99 -ftree-vectorize -marm -mfpu=neon -O3, it uses vld1.16 and vst1.32 regardless of the parameter alignment. This is on armv7a. The gcc version (and the clang version with our modified backend) runs fine, even on 2-byte aligned data. Is this not a guarantee across armv7/armv7a generally? Pete On 09/05/2012 03:15...
2011 Mar 09
5
[LLVMdev] LLVM 2.9 RC1 Pre-release Tarballs
There are LLVM 2.9 RC1 pre-release tarballs source available. You can find them here: http://llvm.org/pre-releases/2.9/ Please download them, build them, and compile things to your heart's content. And most importantly file a bunch of bug reports. :-) Share and enjoy! -bw
2013 Aug 13
13
[PATCH v8 8/5] Add UART support and arch timer initialization for OMAP5
Since OMAP UART has a few distinct features than common 8250 UART, I re-implemented its driver rather than porting it based on ns16550.c. There are mainly two big differences between the implementations. First, OMAP UART introduces the concept of register access mode, which divides the register map into seperated space. Switching the access mode is then necessary when configuring it. Second, THRE
2012 Sep 05
0
[LLVMdev] Unaligned vector memory access for ARM/NEON.
...le this program with clang -O3 -ccc-host-triple armv7-none-linux-gnueabi -mfpu=neon -mllvm -vectorize, the intermediate LLVM assembly > looks OK (and it has an align 2 vector load), but the generated ARM assembly has the scalar loads. > When I compile with (4.6) gcc -std=c99 -ftree-vectorize -marm -mfpu=neon -O3, it uses vld1.16 and vst1.32 regardless of the parameter alignment. This is on armv7a. > > The gcc version (and the clang version with our modified backend) runs fine, even on 2-byte aligned data. Is this not a guarantee across armv7/armv7a generally? > > Pete > &...
2014 Feb 20
0
Wine release 1.7.13
...winebuild: Generate position-independent code for ARM. ntdll: Fix printing formats for ARM registers. kernel32: Set correct binary type for COM and PIF files. widl: Ignore unknown -m target options. wrc: Ignore unknown -m target options. winebuild: Add support for -marm and -mthumb target flags. winegcc: Forward -marm and -mthumb options to winebuild. configure: Add the -marm option to the target flags. ntdll: Trace missing exception info on ARM. kernel32/tests: Add some tests for dll import resolution. ntdll: Don't fixup imports...
2018 Apr 10
1
How to get the case value from Machine Instruction
Thanks for your help. Is there possible I can get the realily case value form the MI? For the case in https://bugs.llvm.org/show_bug.cgi?id=34902. as follows. ############################# * GCC v7.1 generated assembly ############################# ** Options: -Os -marm -march=armv7-a foo: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 sub r0, r0, #15 push {r4, lr} cmp r0, #5 ldrls pc, [pc, r0, asl #2] b .L1 .L4: .word .L3 .word .L5...
2012 Sep 06
2
[LLVMdev] Unaligned vector memory access for ARM/NEON.
...program with clang -O3 -ccc-host-triple armv7-none-linux-gnueabi -mfpu=neon -mllvm -vectorize, the intermediate LLVM assembly >> looks OK (and it has an align 2 vector load), but the generated ARM assembly has the scalar loads. >> When I compile with (4.6) gcc -std=c99 -ftree-vectorize -marm -mfpu=neon -O3, it uses vld1.16 and vst1.32 regardless of the parameter alignment. This is on armv7a. >> >> The gcc version (and the clang version with our modified backend) runs fine, even on 2-byte aligned data. Is this not a guarantee across armv7/armv7a generally? >> >&gt...
2015 Sep 16
3
Arm: disabling/disallowing Thumb instructions
Hi all, When I use Clang, I can add -mno-thumb to the command line and Clang generates pure Arm code without any use of Thumb instructions. However, I am messing about with the Glasgow Haskell Compiler (GHC) which generates LLVM IR code directly and then calls `opt` and `llc` on that IR code. The generated IR code currently has: target datalayout =