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Hello everyone, We are working on extending RISC-V LLVM backend which will help us to achieve the goal of improving programmability in the second generation design of our open source RISC-V manycore processor (bjump.org/manycore). We started with supporting 64 bit pointers in RISCV 32 bit backend using address spaces and register pairs. We aim to support 64 bit pointers in address space 1 using

> > Hi Reshabh, and congratulations on being selected for GSoC. I haven't > looked at supporting larger than native-width pointers on a target > before. I'd thought that AVR might be relevant (given it uses 16-bit > pointers but has 8-bit GPRs). See the description here > <http://lists.llvm.org/pipermail/llvm-dev/2019-January/129089.html>. > Many thanks Alex,

Hey compiler peeps, Cray is ramping up a number of exciting projects and we're looking for new hires. Obviously parallelism has been our core focus, but the challenges of manycore and accelerator technology are presenting new twists requiring us to bring new solutions to bear. After the successful launch of the Jaguar machine (the fastest for open science,

On 26/02/2014 09:03, David Chisnall wrote: > On 25 Feb 2014, at 23:13, Alp Toker <alp at nuanti.com> wrote: > >> Now that we've kick-started the LLVM OpenMP runtime discussion, I want to make a concrete proposal to get a test suite up and running for the LLVM OpenMP runtime. I don't think the current setup as an LLVM subproject is sustainable going forward without some

> Why do you want this? The goal is to share arrays between multiple tiles on a manycore architecture by splitting arrays between tiles. With a DRF memory model, it makes sense to elide multiple loads to the same memory location between barriers.; IIRC the semantics for volatile don’t allow this eliding. -------------- next part -------------- An HTML attachment was scrubbed... URL:

...Creating the %d map',i)); GaussRF(x=x, y=y, model=model, grid=TRUE,param=c(mean,variance,nugget,scale,Whit.alpha)) } ) ) user system elapsed 1816.784 296.745 1062.142 ------------------------------------------- C.Case. Foreach is considered to be easier to be applied to manycores. foreach (i=1:dimz) %do% { print(sprintf('Creating the %d map',i)); Shadowlist[,,i]<-f <- GaussRF(x=x, y=y, model=model, grid=TRUE,param=c(mean,variance,nugget,scale,Whit.alpha)) } user system elapsed 1027.058 13.243 1031.849 -------------------------------...

Hi, David, Is the LLVM-based back end you have been working on for the Cascade system used by this or any other Cray installations? Is the XT5 related to Cascade in any way? Thanks, --Vikram Associate Professor, Computer Science University of Illinois at Urbana-Champaign http://llvm.org/~vadve On Jul 8, 2009, at 3:59 PM, David Greene wrote: > Hey compiler peeps, > > Cray is

All: Sorry if this is a bit off-topic, but... having two successful workshops at Supercomputing, I'm contemplating a third (I'm a glutton for punishment.) This year, the focus will be on many/multicore's programmability gap -- the gap between today's languages and the multicore/manycore architectures that we're trying to program. A stellar example is software development on

On Thu, Jul 11, 2019 at 10:42 PM Tim Northover <t.p.northover at gmail.com> wrote: > On Thu, 11 Jul 2019 at 18:03, Reshabh Sharma <reshabhsh at gmail.com> wrote: > > Ah now I could see it more clearly. I was not sure that should I add > them (MO_LO32_LO and MO_LO32_HI), btw this was backup plan. Probably for > now we are going with this. I implemented them today and

April 7, 2015 Release IEEE International Conference on Cluster Computing September 8-11, 2015 Chicago, IL, USA http://www.mcs.anl.gov/ieeecluster2015/ *** CALL FOR POSTERS *** The IEEE Cluster 2015 provides a forum for both academia and industry professionals to present their latest research findings in all aspects of cluster, cloud, and grid technologies in the form of a posters, which will be

April 7, 2015 Release IEEE International Conference on Cluster Computing September 8-11, 2015 Chicago, IL, USA http://www.mcs.anl.gov/ieeecluster2015/ *** CALL FOR POSTERS *** The IEEE Cluster 2015 provides a forum for both academia and industry professionals to present their latest research findings in all aspects of cluster, cloud, and grid technologies in the form of a posters, which will be

> What's needed for CPU affinity? We expose his via pthread_attr_setaffinity_np() in <pthread_np.h> - > does the runtime need anything more from the interface, or was this support just not yet a high > priority for you? I'd be happy to help with this support. The Linux code uses the sched_{get,set}affinity calls directly, rather than via the pthread veneer. It can also

So, volatile’s been a fine solution — the issue is volatile pointers would perform the load every time; ideally memory accesses would be able to be cached. This is why I’ve been leaning towards disabling the part of instcombine that combines memory accesses instead of using volatile — there should be better performance. On Apr 17, 2019, 9:54 AM -0700, Jameson Nash <vtjnash at gmail.com>,

Now that we've kick-started the LLVM OpenMP runtime discussion, I want to make a concrete proposal to get a test suite up and running for the LLVM OpenMP runtime. I don't think the current setup as an LLVM subproject is sustainable going forward without some form of testing support, automated or otherwise. The motivation: It's difficult to make changes to the source without some

A Proposal for adding an experimental IR-level region-annotation infrastructure ============================================================================= Hal Finkel (ANL) and Xinmin Tian (Intel) This is a proposal for adding an experimental infrastructure to support annotating regions in LLVM IR, making use of intrinsics and metadata, and a generic analysis to allow transformations to