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...str w8, [x0, w1, sxtw #2] ret The sext can be matched as part of the addressing mode for AArch64 – maybe it’s something in codegenprepare for x86 going awry? Cheers, James From: Sanjay Patel [mailto:spatel at rotateright.com] Sent: 26 June 2014 18:11 To: Manjunath DN Cc: James Molloy; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Contributing the Apple ARM64 compiler backend >> We've also seen similar instances where multiple registers are used to compute very similar >> addresses (such as x+0 and x+4!) and this increases register pressur...

....x, <$src1 or $src2>.<something that depends on the mask>" I can use the same modifier trick for which component of the source to select, but I don't know how to select which of the sources to select ($src1 or $src2) depending on the mask. Do you have any suggestions? Thanks, Manjunath On Wed, May 6, 2009 at 10:10 AM, Dan Gohman <gohman at apple.com> wrote: > One way to do this is to handle this in the AsmPrinter, with > operand modifiers. > > For example, on x86 there are instructions with ${dst:call} in > their asm string. The "call" part is inte...

...= void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' failed. I am creating a list of instructions using BuildMI() and adding them to a basic block using BB->insert(). I am seeing this assertion after some number of insertions. Am I doing something wrong? Manjunath

HI James, Thanks for your reply and hints on what can be done for the Aarch64 backend optimization for llvm We have SPEC license and v8 hardware. So I will start looking into it warm regards Manjunath On Wed, Jun 25, 2014 at 8:42 PM, James Molloy <james.molloy at arm.com> wrote: > Hi Manjunath, > > At the time of writing that status we had only done our initial analysis. > This was done without real hardware and attempted to identify poor code > sequences but we were una...

Manjunath, I had a very similar problem and I solved it using a custom vector shuffle and addition instead of mov. For example, Vector_shuffle s1, s2, <0,3> is mapped to a custom instruction where I transform the swizzle to a 32bit integer mask and an inverted mask. So I have dst, src0, src1, imm1,...

...users local profiles only. When the client tries to logon to the PDC it looks for a profile to download where do I put this default profile. Please help me I am totally lost with this error from past two days I tried everything & googled around quite a bit but of no help. Please help me. TIA Manjunath DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the intended recipient (s) only. It may contain proprietary material, confidential information and/or be subject to the legal privilege of iWave Systems Technologies Private Limited. If you have received this message in er...

On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: > I am seeing the following assertion in leak detector. > > /llvm/lib/VMCore/LeakDetector.cpp:43: > void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = > void]: Assertion `Ts.count(Cache) == 0 && "Obje...

...ilist.push_back(mi); } viud insertInto(MachineBasicBlock *BB, MachineBasicBlock::iterator II) { std::vector<MachineInstr *> temp; createInstrs(temp); for(unsigned i=0, e=temp.size(); i!=e; ++i) BB->insert(II, temp[i]); } I am getting the assertion during BB->insert() Manjunath On Wed, Jun 3, 2009 at 5:26 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: >> I am seeing the following assertion in leak detector. >> >> /llvm/lib/VMCore/LeakDetector.cpp:43: >&gt...

...arc etc.. That got me wondering if I am breaking some conventions and not doing things in the LLVM-way. Is what I am trying to do an intended use case for Tablegen? Why aren't there Tablegen backends specific to some architecture backends? I would be grateful for any advice from the community. Manjunath

Eric Christopher <echristo <at> gmail.com> writes: > > > The big pain issues I see merging from ARM64 to AArch64 are: > > 1. Apple have created a fairly complete scheduling model already for > > ARM64, and we'd have to merge the partial? model in AArch64 and theirs. We > > risk regressing performance on Apple's targets here, and we can't

Manjunath, I asked this question recently, but instead of telling you to search the archive I'm going to take it as a chance to recall how to do it (because I'll do so anyway and even telling tablegen to use an enum for instructions is not as trivial to do as you might think : ) I wrote it up in the...

...ction, something like !strconcat("mov $dst, v.", elemnames[$input]). I am still trying to learn the tablegen syntax and semantics, so how to do this is not clear to me. I will appreciate any suggestions on how to do this, or pointers to other places where similar things are done. Thanks, Manjunath

...: vecInst<..., Sub>; ... def ORV4 : vecInst<..., OR>; Now, I can write a tablegen backend that can output a opcode->opcode map, which can be used by the pass. Is this and intended use case for Tablegen? Or, are tablegen backends supposed to be generic to all architecture backends? Manjunath On Mon, Jun 8, 2009 at 1:23 AM, Christian Sayer<Christian.Sayer at dibcom.fr> wrote: > Manjunath, > I asked this question recently, but instead of telling you to search the archive > I'm going to take it as a chance to recall how to do it (because I'll do so anyway > and...

...;call" modifier on MachineOperand::MO_Immediate operands (in X86ATTAsmPrinter::printOperand), which lets it perform custom printing for that type of operand. You could use a modifier which tells the AsmPrinter to print an immediate as the appropriate letter. Dan On May 5, 2009, at 10:23 PM, Manjunath Kudlur wrote: > Hello, > > I am trying to create a machine instruction for "extractelement". I > want to translate > r <- extractelement v, 0 > to > mov r, v.x > > I was looking at the dag I can use and I found vector_extract. The > inputs for this SDnode...

...and add every user to it. Then change the ownership of the profiles directory. Also make sure that all of your users have R/W permissions on that directory. Regards, Robert Adkins II IT Manager/Buyer Impel Industries, Inc. Ph. 586-254-5800 Fx. 586-254-5804 -----Original Message----- From: Manjunath H N [mailto:manjunath@iwavesystems.com] Sent: Monday, February 03, 2003 5:37 PM To: samba@lists.samba.org; Robert Adkins Subject: [Samba] Not able to login to Samba PDC. Hello All, I am getting Windows cannot create profile directory, when I try to log on to the Samba PDC, on Win2K m/c A...

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...->getRegUseDefListHead(getReg()) for the new register is 0xffffffff somehow. I suspect I am not following some rules when adding the instructions to a basic block. I would be grateful if some one can point out what I am doing wrong, and provide suggestions on how to go about doing this. Thanks, Manjunath

...I created the directory /usr/local/samba/profiles, but when I try to logon to my Samba PDC these is the error that is being logged. [2003/02/01 13:53:08, 0] smbd/service.c:make_connection(252) iwave-123 (192.168.2.157) couldn't find service profiles Any help on this highly appreciated. TIA Manjunath H N DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the intended recipient (s) only. It may contain proprietary material, confidential information and/or be subject to the legal privilege of iWave Systems Technologies Private Limited. If you have received this message in...

...can be matched as part of the addressing mode for AArch64 – maybe it’s something in codegenprepare for x86 going awry? > > > > Cheers, > > > > James > > > > From: Sanjay Patel [mailto:spatel at rotateright.com] > Sent: 26 June 2014 18:11 > To: Manjunath DN > Cc: James Molloy; llvmdev at cs.uiuc.edu > > > Subject: Re: [LLVMdev] Contributing the Apple ARM64 compiler backend > > > > >> We've also seen similar instances where multiple registers are used to compute very similar > >> addresses (such as x+...

...r_shuffle v2f32Reg:$src1, v2f32Reg:$src2, (build_vector imm:$c1, imm:$c2))) Table gen barfs about type inference contradiction for build_vector. What am I doing wrong and how can I achieve converting to the aforesaid machine instruction? Thanks, Manjunath