search for: managed_falcons_nam

Hi Alexandre, On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: [snip] > +static const char * > +managed_falcons_names[] = { > + [NVKM_SECBOOT_FALCON_PMU] = "PMU", > + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", "<reserved>" perhaps ? we already have one invalid below. > + [NVKM_SECBOOT_FALCON_FECS] = "FECS", > + [NVKM_SECB...

...:13, Ben Skeggs <skeggsb at gmail.com> wrote: > On 01/21/2016 10:09 PM, Emil Velikov wrote: >> Hi Alexandre, >> >> On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: >> >> [snip] >>> +static const char * >>> +managed_falcons_names[] = { >>> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >>> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", >> "<reserved>" perhaps ? we already have one invalid below. > Does <reserved> really mean: "we don't...

On 01/21/2016 10:09 PM, Emil Velikov wrote: > Hi Alexandre, > > On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: > > [snip] >> +static const char * >> +managed_falcons_names[] = { >> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", > "<reserved>" perhaps ? we already have one invalid below. Does <reserved> really mean: "we don't want to tell you?...

...mail.com> wrote: >> On 01/21/2016 10:09 PM, Emil Velikov wrote: >>> Hi Alexandre, >>> >>> On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: >>> >>> [snip] >>>> +static const char * >>>> +managed_falcons_names[] = { >>>> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >>>> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", >>> "<reserved>" perhaps ? we already have one invalid below. >> Does <reserved> really mean: &qu...

...ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "priv.h" +#include <subdev/timer.h> + +static const char * +managed_falcons_names[] = { + [NVKM_SECBOOT_FALCON_PMU] = "PMU", + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", + [NVKM_SECBOOT_FALCON_FECS] = "FECS", + [NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS", + [NVKM_SECBOOT_FALCON_END] = "<invalid>", +}; + +/* + * Helper...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,