search for: machinetracemetr

This conflict is with many optimizations incl. copy prop, coalescing, hoisting etc. Each could increase register pressure and with similar impact. Attempts to control the register pressure locally (within an optimization pass) tend to get hard to tune and maintain. Would it be a better way to describe eg in metadata how to undo an optimization? Optimizations that attempt to reduce pressure like

...hineFunction - MachineFunctionPass - MachineFunctionPrinterPass - MachineInstrBundle - MachineInstr - MachineLICM - MachineLoopInfo - MachineModuleInfo - MachineModuleInfoImpls - MachinePassRegistry - MachinePostDominators - MachineRegisterInfo - MachineScheduler - MachineSink - MachineSSAUpdater - MachineTraceMetrics - MachineVerifier Are there any files in this list that should not be moved? Any others that should be added? Any suggestions on which of these modules would be a good place to start? One question of procedure... Back in 2010 and 2011, I had commit rights on the LLVM svn repository because of...

The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. In this case, we probably need a profitability target hook which knows about lea. We should also consider disabling it's dumb pseudo scheduling code when we enable MI scheduler. Evan Sent from my iPad > On Oct...

Ping From: Mandeep Singh Grang [mailto:mgrang at codeaurora.org] Sent: Tuesday, February 03, 2015 4:34 PM To: 'llvmdev at cs.uiuc.edu' Cc: 'ghoflehner at apple.com'; 'apazos at codeaurora.org'; mgrang at codeaurora.org Subject: Question on Machine Combiner Pass Hi, In the file lib/CodeGen/MachineCombiner.cpp I see that in the function

Hi All, I'm tring to use RSQRT instructions on follow case for ARM (now what using is sqrt): 1.0 / sqrt(x) The RSQRT instructions(VRSQRTE/VRSQRTS) are vector type, but above operation is scalar type. So a transformation must be done(transform sqrt pattern to rsqrt). I have completed a patch for this, but I made the transformation in the backend which will leads to additional

Hi, > > Sorry to dig up an old thread but I wondered what the status of > if-conversion in LLVM is. Has any work been done towards handling this as a > transform pass on the IR? > As far as I know, some if-conversion is done in SimplifyCFG: Have a look at the SpeculativelyExecuteBB function in lib/Transforms/Utils/SimplifyCFG.cpp. Cheers, Jonas -------------- next part

...gt; - MachineInstrBundle > - MachineInstr > - MachineLICM > - MachineLoopInfo > - MachineModuleInfo > - MachineModuleInfoImpls > - MachinePassRegistry > - MachinePostDominators > - MachineRegisterInfo > - MachineScheduler > - MachineSink > - MachineSSAUpdater > - MachineTraceMetrics > - MachineVerifier I *think* the goal here is to minimize the amount of code that gets linked into certain machine-code level tools. If that is the goal, then you only want the modules for Machine IR, and maybe some core analysis passes. The “Machine” modules you listed above include machi...

On Oct 2, 2013, at 11:48 PM, Evan Cheng <evan.cheng at apple.com> wrote: > The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. > > In this case, we probably need a profitability target hook which knows about lea. We should also consider disabling it's dumb pseudo scheduling code when we enable MI scheduler. Sorry, I set this aside to...

Hi LLVM community, Currently LLVM backend do pre-RA machine instruction scheduling in non-SSA form, I doubt why not do machine scheduling in SSA machine instruction form? Now LLVM’s machine scheduling uses a list-scheduling algorithm, but if we wang to support more complex scheduling algorithms, for example, modulo scheduling for loops, it seems more easy to accomplish this in SSA form as SSA is

This sounds like llvm.org/pr13320. On 17 September 2013 18:20, Bader, Aleksey A <aleksey.a.bader at intel.com> wrote: > Hi all. > > > > I’m looking for an advice on how to deal with inefficient code generation > for Intel Nehalem/Westmere architecture on 64-bit platform for the attached > test.cpp (LLVM IR is in test.cpp.ll). > > The inner loop has 11 iterations

Also you might need to check use PostRASchedulerList or PostMachineScheduler, PostRASchedulerList is considered deprecated as mentioned in [1]. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-April/112348.html HTH, chenwj 2017-06-10 4:03 GMT+08:00 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw>: > Not saying I am totally understand how thing works, but I think you're > misleading >

Hi all. I'm looking for an advice on how to deal with inefficient code generation for Intel Nehalem/Westmere architecture on 64-bit platform for the attached test.cpp (LLVM IR is in test.cpp.ll). The inner loop has 11 iterations and eventually unrolled. Test.lea.s is the assembly code of the outer loop. It simply has 11 loads, 11 FP add, 11 FP mull, 1 FP store and lea+mov for index

...ase+Asserts build llvm[2]: Compiling MachineRegisterInfo.cpp for Release+Asserts build llvm[2]: Compiling MachineSSAUpdater.cpp for Release+Asserts build llvm[2]: Compiling MachineScheduler.cpp for Release+Asserts build llvm[2]: Compiling MachineSink.cpp for Release+Asserts build llvm[2]: Compiling MachineTraceMetrics.cpp for Release+Asserts build llvm[2]: Compiling MachineVerifier.cpp for Release+Asserts build llvm[2]: Compiling OcamlGC.cpp for Release+Asserts build llvm[2]: Compiling OptimizePHIs.cpp for Release+Asserts build llvm[2]: Compiling PHIElimination.cpp for Release+Asserts build llvm[2]: Compiling...