search for: machinesdnod

Hi all, I need to figure out why InstrEmitter::EmitMachineNode assumes that when the number of outputs of a MachineSDNode is greater than the number of defs in the corresponding MCInstrDesc, the outputs in the difference will be placed into physical registers as opposed to virtual registers. The specific line in question is: bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;...

On Nov 9, 2011, at 2:12 PM, Chris Lattner wrote: > On Nov 9, 2011, at 1:08 PM, Jim Grosbach wrote: >>> On Nov 9, 2011, at 10:49 AM, Jim Grosbach wrote: >>>>> >>>>> It's not good, but people do it. Also constructing enums via & and | etc. It'd be nice to be able to get the name of whatever it is that the code generator actually produced :)

...adSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); cast<MachineSDNode>(LDW)->setMemRefs(MemOp, MemOp + 1); // Reshuffle LDW's results so that the first two match LOAD's result // type S...

Hi Jochen, > My llvm version is 3.0 release. > I have a module generated by clang. When I optimize it, I first add an > inlining pass (llvm::createFunctionInliningPass), then these passes: > - own FunctionPass > - llvm::createPromoteMemoryToRegisterPass > - llvm::createInstructionCombiningPass > - llvm::createDeadInstEliminationPass > - llvm::createDeadStoreEliminationPass

Hi! My llvm version is 3.0 release. I have a module generated by clang. When I optimize it, I first add an inlining pass (llvm::createFunctionInliningPass), then these passes: - own FunctionPass - llvm::createPromoteMemoryToRegisterPass - llvm::createInstructionCombiningPass - llvm::createDeadInstEliminationPass - llvm::createDeadStoreEliminationPass - new llvm::DominatorTree() - new

...sical > register. > > Cheers, > -Quentin > > On Nov 18, 2019, at 6:21 PM, Thomas Lively via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I need to figure out why InstrEmitter::EmitMachineNode assumes that when > the number of outputs of a MachineSDNode is greater than the number of defs > in the corresponding MCInstrDesc, the outputs in the difference will be > placed into physical registers as opposed to virtual registers. > > The specific line in question is: > bool HasPhysRegOuts = NumResults > NumDefs && > II...

...rn values, this approach would require generating billions of Instructions in TableGen. So that won't work. The other approach is to have just one call instruction that has variadic outputs as well as inputs. This is the approach I am pursuing now, and I have it working through the lowering to MachineSDNodes, but the approach is breaking down in the InstrEmitter because it is trying to use physical registers. WebAssembly is a stack machine, so all instructions including calls push their results onto the value stack as opposed to placing them in registers. The value stack is not in memory and not add...

...130<Mem:ST1[@s]> [ID=4] // This is a store to s Underlying Values: @q = common global i8* null, align 4 @s = common global i8 0, align 1 The way inquiry is made is similar to DAGCombiner::isAlias() SDNode *SDN1; SDNode *SDN2; MachineMemOperand *MMOa; MachineMemOperand *MMOb; ... const MachineSDNode *MNb = dyn_cast<MachineSDNode>(SDN2); const MachineSDNode *MNa = dyn_cast<MachineSDNode>(SDN1); ... MMOa = !MNa->memoperands_empty() ? (*MNa->memoperands_begin()) : NULL; MMOb = !MNb->memoperands_empty() ? (*MNb->memoperan...

Hello. I expand an instruction to a sequence of MachineSDNodes at instruction selection, in the Select() method of the SelectionDAGISel class. For efficiency, in order to generate fewer instructions, I would like to assign twice to the same physical register - but since I don't want to "mess" with the register allocator, I am using only...

...would > require generating billions of Instructions in TableGen. So that won't work. > > The other approach is to have just one call instruction that has variadic > outputs as well as inputs. This is the approach I am pursuing now, and I > have it working through the lowering to MachineSDNodes, but the approach is > breaking down in the InstrEmitter because it is trying to use physical > registers. > > WebAssembly is a stack machine, so all instructions including calls push > their results onto the value stack as opposed to placing them in registers. > The value stack...

...below) which added this to SIISelLowering.cpp: // Adjust the writemask in the node std::vector<SDValue> Ops; Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) Ops.push_back(Node->getOperand(i)); Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); That fails with Leopard's libstdc++ STL which does not a data method for std::vector. This method was added in C++11: http://www.cplusplus.com/reference/vector/vector/ Is llvm-3.4 now requiring a C++11 runtime? If not, can we solve thi...

...DNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); > > // Honestly, I have no idea what this does, but other memory > // accessing instructions have something similar... > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); > MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); > cast<MachineSDNode>(LDW)->setMemRefs(MemOp, MemOp + 1); > > // Reshuffle LDW's results so that the first two match LOAD's > result &...

...owering.cpp: > > // Adjust the writemask in the node > std::vector<SDValue> Ops; > Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); > for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) > Ops.push_back(Node->getOperand(i)); > Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); > > That fails with Leopard's libstdc++ STL which does not a data method for std::vector. This method was added in C++11: > http://www.cplusplus.com/reference/vector/vector/ > > Is llvm-3.4 now requiring a C++11 runtime? I...

I am implementing a new backend and am pretty sure I don't quite understand "the way" one is supposed to implement conditional branches. My target CPU natively supports a conditional branch instruction that accepts a condition to test (equal, less than, etc.), two operands (two registers, or one register and one immediate), and finally a target PC to branch to if the comparison

...>> // Adjust the writemask in the node >> std::vector<SDValue> Ops; >> Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); >> for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) >> Ops.push_back(Node->getOperand(i)); >> Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); >> >> That fails with Leopard's libstdc++ STL which does not a data method for std::vector. This method was added in C++11: >> http://www.cplusplus.com/reference/vector/vector/ >> >> Is llvm-3.4 now requiri...

Hello. Because I experience optimizations (DCE, OoO schedule) which mess the correct semantics of the list of instructions lowered in ISelLowering from the VSELECT LLVM instruction, and these bad transformations happen even before scheduling, at later I-sel subpasses, I try to fix this problem by lowering VSELECT to only one pseudo-instruction and LATER translate it to a list of

On Mon, Jun 6, 2016 at 8:32 AM, Nemanja Ivanovic via llvm-dev <llvm-dev at lists.llvm.org> wrote: > It is not a keyword. It is a node defined in > include/llvm/Target/TargetSelectionDAG.td. You can likely find most of the > definitions you're wondering about there. > In terms of its purpose, perhaps someone can elaborate on that a bit more, > but there is no corresponding

Hello. I am using the post-RA (Register Allocation) scheduler to avoid data hazards by inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart some sequences of instructions which should remain "glued" together. More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for example a BUILD_VECTOR with a machine SDNode called

Hello. I'm having problems at instruction selection with my back end with the following basic-block due to a vector add with immediate constant vector (obtained by vectorizing a simple C program doing vector sum map): vector.ph: ; preds = %vector.memcheck50 %.splatinsert = insertelement <8 x i64> undef, i64 %i.07.unr, i32 0