search for: machinescheduler

I think those should be considered internal options for (llvm codegen) developers, a normal compiler user should not need to use any of them. Of course you can look around the llvm sourcecode (esp. in lib/CodeGen/MachineScheduler.cpp) and see what cl::opt options are available and how they affect the scheduler operation. In case of the MachineScheduler all settings are the same regardless of the optimisation level, however the MachineScheduler is disabled as a whole in TargetPassConfig.cpp when optimized regalloc is not en...

...placement, I often see unnecessary unconditional jumps. So I'm not sure what is considered best practice. Hopefully someone else on the list will clarify. Either way it is definitely not an assumption made by the scheduler. In my previous message, I was pointing out corner cases present in the MachineScheduler::runOnMachineFunction loop--they all have to do with terminators or lack thereof. It is interesting to note that a VLIW target will want to do block placement before final bundling. That's not something I plan to fix short term. I think you can deal with it in your target's pass config and...

Hi, I'm trying to understand why MachineScheduler does a poor job in straight line code in cases like the one in the attached debug dump. This is on AMDGPU, an in-order target, and the problem is that the IMAGE_SAMPLE instructions have very high (80 cycle) latency, but in the resulting schedule they are often placed right next to their uses like t...

...g my bachelor thesis. The topic is about the implementation and evaluation of trace scheduling in the llvm framework for VLIW architecture. Simplifying the problem, only loop free code will be processed. Further, preparations and studies of llvm framework have shown, that, in my humble opinion, the machineScheduler::runOnMachineFunction() would be the best place to start with. Later the code will be put into a separate class like the HexagonMachineScheduler and the MachineScheduler will be reverted back to it's original state. This is an outline of my concept on how to implement this basic trace schedulin...

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has 256 registers, but there is a significant performa...

...t why the compilation is failing. There is a lot of output and at this point I'm not sure what is important and what is not. I'm trying to solve this problem in small steps, so if asked I can certainly provide more information. The first error that I see during compilation is lib/CodeGen/MachineScheduler.cpp:1165: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit*, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Another important detail is that we are running clang-3.5. I know it is old, but for now we are not allowed to switch to a newer ve...

...getting the job done for you (innefficiently in terms of compile time). > In the PostRA scheduler, is there any way to represent the "throughput" (the number of cycles which must elapse before an instruction of the same type can start) of an instruction? The new model that works with MachineScheduler (not PostRA) lets you specify throughput in two dimensions, horizontally as a functional unit list, and vertically as a ResourceCycles attribute. Horizontal: def : WriteRes<WriteTwoPorts, [Port1, Port2]>; Vertical: def : WriteRes<WriteTwoCycles, [Port1]> { let ResourceCycles = [2];...

...MicroOpBufferSize = 1. Re "issue limited" and instruction groups: could it make sense to disable the generic scheduler's detection of issue limitation on in-order CPUs, or on CPUs that don't define instruction groups, or some similar condition? Something like: --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -2062,10 +2062,13 @@ getOtherResourceCount(unsigned &OtherCritIdx) { if (!SchedModel->hasInstrSchedModel()) return 0; - unsigned OtherCritCount = Rem->RemIssueCount - + (RetiredMOps * SchedModel->getMicroOpFactor()); - LLVM_DE...

On Jul 22, 2013, at 11:50 AM, Tom Stellard <tom at stellard.net> wrote: > Hi, > > I'm working on defining a SchedMachineModel for the Southern Islands > family of GPUs, and I have two questions related to the > MachineScheduler. > > 1. I have a resource that can process 15 instructions at the same time. > In the TableGen definitions, should I do: > > def HWVMEM : ProcResource<15>; > or > > let BufferSize = 15 in { > def HWVMEM : ProcResource<1>; > } For in-order processors y...

I'm briefly enabling the MachineScheduler pass for x86 tonight to collect information on any failures that may show up. To properly enable the new scheduler, this hook is implemented in X86Subtarget: bool enableMachineScheduler() const LLVM_OVERRIDE { return true; } The MachineScheduler pass itself can be enabled/disabled with -enable...

Thanks that clears things up. So if I want to mess around with how schedules are generated, looking at the MachineScheduler pass is the best place now? -Dilan On Mon, Jul 31, 2017 at 3:24 PM Matthias Braun <mbraun at apple.com> wrote: > > > On Jul 31, 2017, at 2:51 PM, Dilan Manatunga via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > I was looking...

I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: -misched-topdown -misched-bottomup The description in MachineScheduler.cpp says: "Force top-down list scheduling" and "Force bottom-up list scheduling" Which isn't too helpful - where might I want to use these? Under what conditions might they improve an instruction schedule? Similar questions for the instruction scheduler strategies: -misc...

Hi Andy, >> Right now it seems that BeginGroup/EndGroup is only used by SystemZ, >> or? I see they are used in checkHazard(), which I actually don't see >> as helpful during pre-RA scheduling for SystemZ. Could this be made >> optional, or perhaps only done post-RA if target does post-RA >> scheduling? SystemZ does post-RA scheduling to manage decoder

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

..., either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required until SD and PostRA schedulers are replaced by MachineScheduler. This poses several question as to: 1) which representation gives the better cost estimation? 2) AFAIK, MachineScheduler can also take advantage from InstrItineraries with the ScoreboardHazardRecognizer for better cost estimation and scheduling. What is the reasoning for having scheduling informa...

Hi to everyone, while working with the machine scheduler for a personal project, I came up with the necessity of inserting a backup boundary in the MachineSchedulerStrategy -- specifically, the PostGenericScheduler -- to hold a copy the scheduler's state, in order to implement a really trivial (and really inefficient) backtracking mechanism. This approach leads to a subtle "segmentation fault", when the pass ends and invokes the deleter. The re...

On Mon, Jun 24, 2013 at 2:41 AM, Andrew Trick <atrick at apple.com> wrote: > I'm briefly enabling the MachineScheduler pass for x86 tonight to collect > information on any failures that may show up. > > To properly enable the new scheduler, this hook is implemented in > X86Subtarget: > > bool enableMachineScheduler() const LLVM_OVERRIDE { return true; } > > The MachineScheduler pass itself...

...nvergingVLIWScheduler::SchedCandidate&) + 284 14 clang-3.5 0x0000000000e4f2e5 llvm::ConvergingVLIWScheduler::pickNodeBidrectional(bool&) + 285 15 clang-3.5 0x0000000000e4f5b0 llvm::ConvergingVLIWScheduler::pickNode(bool&) + 576 16 clang-3.5 0x0000000000e4db8e llvm::VLIWMachineScheduler::schedule() + 1366 17 clang-3.5 0x0000000001d7830f 18 clang-3.5 0x0000000001d77988 19 clang-3.5 0x0000000001d4f9c7 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95 20 clang-3.5 0x00000000014dacee llvm::FPPassManager::runOnFunction(llvm::Function&) + 290...

> On May 14, 2018, at 11:10 AM, Jonas Paulsson <paulsson at linux.vnet.ibm.com> wrote: > > Hi Andrew, > > Thank you very much for the most helpful explanations! Many things could go in as comments, if you ask me - for example: > > --- >> The LLVM machine model is an abstract machine. > >> The abstract pipeline is built around the notion of an

...I assume you are totally decoupled from what LLVM currently calls the "postRA" scheduling pass. Hopefully you don't need anything in PostRASchedulerList.cpp. Running your bundler as a preEmit pass is the cleanest approach. But if need be, we can support preRA bundling at the time the MachineScheduler currently runs (if enabled). TargetPassConfig allows you to substitute your own pass in place of MachineScheduler. Passes that run after MachineScheduler are intended to support instruction bundles. This feature is not extensively tested, so anyone taking this approach would need to work with backe...