search for: machineschedstrategy

...| v ScheduleDAGMI: Concrete implementation that supports both top-down and bottom-up scheduling with live interval update. It divides the region into three zones: Top-scheduled, bottom-scheduled, and unscheduled. The ScheduleDAGMI constructor takes an instance of MachineSchedStrategy. This is currently a very simply interface that provides pickNode(), releaseTopNode(), releaseBottomNode(). The MachineScheduler is plugable at every level. 1. The pass itself is optional. Targets may disable or override it completely. For example, a target that implements global scheduling...

...would be a good time to try switching over and start filing bugs. PPC is an example of using MI scheduler out-of-box. Hexagon is an example of customizing it at a high level. You could start off like PPC with minimal customization, but eventually you may want something in between--provide a custom MachineSchedStrategy: class MyScheduler : public MachineSchedStrategy {...} namespace llvm { ScheduleDAGInstrs *createMySched(MachineSchedContext *C) { ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new MyScheduler()); DAG->addMutation(new MyDAGMutation()); return DAG; } } // namespace llvm static MachineSchedRe...

...try switching over and start filing bugs. > PPC is an example of using MI scheduler out-of-box. Hexagon is an > example of customizing it at a high level. You could start off like > PPC with minimal customization, but eventually you may want something > in between--provide a custom MachineSchedStrategy: > > class MyScheduler : public MachineSchedStrategy {...} > > namespace llvm { > ScheduleDAGInstrs *createMySched(MachineSchedContext *C) { > ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new MyScheduler()); > DAG->addMutation(new MyDAGMutation()); > return DAG; > }...

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

Hey Everyone, I'd like to begin a project to rework the scheduler to address some problems we've discovered on this end. The goal is to get a more configurable/flexible scheduler while simplifying maintenance by separating policy from implementation to get independent and interchangeable parts. This is going to be challenging because we are still stuck on LLVM 2.9. We will be upgrading

I have an instruction that takes no operands, and produces two results, in two consecutive cycles. I tried both of the following to my Schedule.td file: InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>, From what I can see in examples, these say that the first

On Jun 3, 2013, at 9:42 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > Hi Jakob, > > thanks for the advice. I'll do as you suggest and make sure that CCR is never live. > > I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of

...(this isn't strictly true but I'll come back to that), and when it has two it dispatches one to ALQ and the other to AGQ. No. The machine model is used to form a scheduling DAG independent of the original schedule. If it's important to be this precise, then I suggest you plugin a new MachineSchedStrategy where you can model stalls for any special cases during scheduling. You need a super-resource: def P5600A : ProcResource<2>; def P5600AGQ : ProcResource<1> { let Super = P5600A; } def P5600ALQ : ProcResource<1> { let Super = P5600A; } I'll take a look at MachineSchedStrateg...

...without interlock, which I think means the port resources should have 'Buffered = 0' in the definition. Is that correct? >> >> Yes, but it isn’t sufficient. The scheduler makes no attempt to insert nops currently. However, at the very least, you will want to implement your own MachineSchedStrategy. It would be natural to handle nop insertion within your implementation. > Nop insertion during scheduling sounds good to me, but nop insertion after regalloc has the advantage of being able to insert nops for spill/reload. Unless you don’t have spills? To elaborate a bit more, MachineSchedule...

Hi Jakob, thanks for the advice. I'll do as you suggest and make sure that CCR is never live. I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of cmp instruction so I might need a lot of pseudos. That's what led me to wonder whether MachineInstrBundles might be a

...cess is static and without interlock, which I think means the port resources should have 'Buffered = 0' in the definition. Is that correct? Yes, but it isn’t sufficient. The scheduler makes no attempt to insert nops currently. However, at the very least, you will want to implement your own MachineSchedStrategy. It would be natural to handle nop insertion within your implementation. In fact, the interpretation of most machine model properties (MircoOpBufferSize, resource BufferSize, ResourceCycles, ResourceDelay) is handled within the MachineSchedStrategy. In past emails I have been explaining how the Ge...

...ar the top-down scheduler will get some attention. We'll be wanting to use that. > As much as possible, the standard scheduling algorithm will be built > from standalone utilities and data structures. The customizations that > you describe would all be handled by providing a new > MachineSchedStrategy. Makes sense to me. > Start by composing your scheduler from the pieces that are available, > e.g. HazardChecker, RegisterPressure... (There's not much value > providing a scheduling queue abstraction on top of vector or > priority_queue). What do you mean by this last point?...

...ng with the MachineScheduler pass. There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse ScheduleDAGMI directly and only define their own MachineSchedStrategy. > > - Our SPEC testing on x86-64 has shown a significant performance improvement of LLVM 3.3 relative to LLVM 2.9 (about 5% in geomean on INT2006 and 15% in geomean on FP2006), but our spill code measurements have shown that LLVM 3.3 generates significantly more spill code on most benchmar...

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that

...ng with the MachineScheduler pass. There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse ScheduleDAGMI directly and only define their own MachineSchedStrategy. > >- Our SPEC testing on x86-64 has shown a significant performance improvement of LLVM 3.3 relative to LLVM 2.9 (about 5% in geomean on INT2006 and 15% in geomean on FP2006), but our spill code measurements have shown that LLVM 3.3 generates significantly more spill code on most benchma...

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,

...th the MachineScheduler pass. > There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse ScheduleDAGMI directly and only define their own MachineSchedStrategy. > >> >> - Our SPEC testing on x86-64 has shown a significant performance improvement of LLVM 3.3 relative to LLVM 2.9 (about 5% in geomean on INT2006 and 15% in geomean on FP2006), but our spill code measurements have shown that LLVM 3.3 generates significantly more spill code on...